Power semiconductor device and method therefor

ABSTRACT

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

This application is a continuation of U.S. application Ser. No.14/685,785, filed Apr. 14, 2015, which is a continuation of U.S.application Ser. No. 13/903,366, filed May 28, 2013, now U.S. Pat. No.9,029,946, issued May 12, 2015, which is a divisional of U.S.application Ser. No. 11/387,210, filed Mar. 23, 2006, now U.S. Pat. No.8,471,378, issued Jun. 25, 2013, which is a divisional of U.S.application Ser. No. 10/557,135 (abandoned), filed Nov. 17, 2005, whichis a National Stage of PCT/US2005/000205 filed on Jan. 6, 2005, whichclaims priority to U.S. Provisional Application 60/535,955, filed Jan.10, 2004 and U.S. Provisional Application 60/535,956, filed Jan. 10,2004 all of which are incorporated herein by reference in theirentirety.

TECHNICAL FIELD

The present disclosure generally relates to a silicon semiconductordevice, and more particularly relates to a radio frequency (RF) powertransistor.

BACKGROUND

The present disclosure relates, in general, to radio frequency (RF)power transistors, and more particularly, to radio frequency (RF) powertransistors operating at a frequency greater than 500 megahertz anddissipating more than 5 watts of power. However, it should be understoodthat certain aspects of this invention have applicability at frequenciesbelow 500 MHz and below 5 Watts. For example, it could find particularutility in power supply and power management circuitry, as well.Therefore, the term “radio frequency (RF) power semiconductor device” or“radio frequency (RF) power transistor” as used in this specificationshould not be construed as limiting the invention unless the claimsspecifically recite such limitations.

The number of wireless applications has grown significantly over thepast decade. The cellular telephone market is among the most pervasiveof wireless technologies. The use of wireless devices is no longerconsidered a luxury but has become a necessity in the modern world.Wireless is by no means limited to cellular applications. Local areanetworks, digital television, and other portable/non-portable electronicdevices are all moving towards having wireless interconnect. Not onlyare the number of different types of wireless devices increasing butthere is also a need for higher data content that can be transmitted andreceived. Increasing the content being delivered requires more bandwidthto transmit the data at a rate that is usable for the customer. Forexample, it is well known that most cellular telephones are currentlyoperating with 2G (2 ^(nd) generation) or 2.5G wireless infrastructure.Second generation wireless (2G) is known for the conversion from analogto digital technology for voice applications. The 2G and 2.5G wirelessinfrastructure has limited capability to send large amounts of data orinformation to a user.

Third generation cellular (3G) is an upgrade in cellular transmissioncapabilities to meet the demands for the transmission of higher content.An example of the higher content includes video information and realtime access to the internet. One area of licensed spectrum that will beutilized for 3G is at a frequency of 2.1 GHz which will be deployedhaving a minimum of 144 kbps packet-data service. Furthermore, there areplans for an enhanced 3G that requires transmission in the 2.6-2.8 GHzrange. Although 4G has not been defined, it is predicted that higherfrequency operation will be required to provide the bandwidth needed forhigh data rate transmission. In particular, it is expected that 4Gwireless transmission will be at frequencies greater than 3 GHz.

There are similar changes occurring in areas other than cellular, suchas television transmission where the conversion to digital television ismandated by the federal government within the next decade. Thesimultaneous transmission of high definition television (HDTV) furtherincreases the complexity of the RF transmission equipment. Another areathat is rapidly expanding wireless activity is wireless broadband foraccess to the internet. What all of these applications have in common isthe use of RF power transistors in power amplifiers (PA) that provide apower output from 5 watts to kilowatt levels.

The move to high frequency and high power transmission places enormousdemands on the RF power transistor. RF power transistors are typicallyused in output stages of transmitters, for example in cellular basetransceiver stations (BTS). The operating frequency for a cellular BTScan be as low as 450 MHz and as high as 2.7 GHz at this time. The poweroutput of a cellular BTS is typically 5 watts and above. Moreover, thewireless industry is moving to standards that require better linearityand lower distortion at the higher frequency of operation. Wirelessinterface technologies such as WCDMA (wideband code division multipleaccess) and OFDM (orthogonal frequency division multiplexing) requirehigh linearity to maximize data throughput and prevent spurious signalsfrom being transmitted outside the transmission band.

The RF power transistor is typically used in a grounded sourceconfiguration. The predominant device being used for this type of highpower radio frequency application has severe device design constraintswhen attempting to further extend frequency, operating voltage, andlowering distortion. Furthermore, thermal issues of the RF powertransistor are as important as electrical design in a RF power amplifierand must be addressed for higher power and higher frequency operation.

Accordingly, it is desirable to provide a RF power transistor thatoperates at higher frequencies with increased linearity. In addition, itis desirable to provide a RF power transistor that is simple tomanufacture and lower in cost. It would be of further benefit if the RFpower transistor had improved thermal management, higher voltageoperation and reduced parasitics.

BRIEF SUMMARY

Various aspects of this invention can be used alone or in combinationwith one another. For example, if it is desired to make a RF powertransistor for cellular applications then many of the improvementsdisclosed herein in both the die manufacture and the package designshould preferably be considered. On the other hand, one or more of theimprovements can be used alone if the application requirements are notso demanding. Furthermore, other desirable features and characteristicsof the present invention will become apparent from the subsequentdetailed description and the appended claims, taken in conjunction withthe accompanying drawings and the foregoing technical field andbackground.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will hereinafter be described in conjunction withthe following drawing figures, wherein like numerals denote likeelements, and

FIG. 1 is a top view of a radio frequency (RF) power transistor die madein accordance with the present invention;

FIG. 2 is a cross-sectional view of the radio frequency (RF) powertransistor die of FIG. 1;

FIGS. 3-21 are exploded cross-sectional views of a portion of the RFpower transistor of FIG. 2 illustrating wafer processing steps to formthe device in accordance with the present invention;

FIG. 22 is a doping profile of a Prior Art RF power transistor;

FIG. 23 is a doping profile of the RF power transistor of FIG. 21 inaccordance with the present invention;

FIG. 24 is a top view of a mesh transistor cell that can be arrayed toform a larger composite structure in accordance with the presentinvention;

FIG. 25 is a top view of an array of mesh transistor cells formed fromthe mesh transistor cell of FIG. 24 in accordance with the presentinvention;

FIG. 26 is a top view of a Prior Art semiconductor package for a RFpower transistor;

FIG. 27 is a top view of a radio frequency (RF) power transistor inaccordance with the present invention;

FIG. 28 is a cross-sectional view of the radio frequency powertransistor die of FIG. 27;

FIG. 29 is a top view of a radio frequency (RF) power transistor packagein accordance with the present invention;

FIG. 30 is cross-section of a portion of the radio frequency powertransistor package of FIG. 29;

FIG. 31 is a top view of FIG. 30;

FIG. 32 is a cross-sectional view of the RF power transistor package ofFIG. 29 in accordance with the present invention;

FIG. 33 is an enlarged cross-sectional view of a portion of the RF powertransistor package illustrated in FIG. 32;

FIG. 34 is a further magnified view of the RF power transistor packageof FIG. 33;

FIGS. 35-38 are cross sectional views of a semiconductor packageaccording to another embodiment of the present invention;

FIG. 39 is a simplified enlarged partial cross-sectional view showingthe various interconnections between the die and the leads of thepackage, in accordance with the teachings of the present invention;

FIG. 40 is a simplified partial top plan view of the device of FIG. 39;

FIG. 41 is a top plan view of a mesh connected cell that can be arrayedto form a larger composite structure, in accordance with an embodimentof this invention;

FIG. 42 is a top plan view of a mesh connected transistor cell that canbe arrayed to form a larger composite structure, in accordance with analternative embodiment of the present invention;

FIG. 43 is a top plan view of a semiconductor die made in accordancewith an alternative embodiment of the present invention;

FIG. 44 is a top plan view of still another embodiment of asemiconductor die made in accordance with the teachings of the presentinvention;

FIG. 45 is a top plan view of the die of FIG. 44 at a subsequentprocessing stage; and

FIG. 46 is an enlarged view of portions of the die of FIG. 45.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and isnot intended to limit the invention or the application and uses of theinvention. Furthermore, there is no intention to be bound by anyexpressed or implied theory presented in the preceding technical field,background, brief summary or the following detailed description.

The Die

Turning now to the drawings, in which like reference characters indicatecorresponding elements throughout the several views, attention is firstdirected to FIG. 1 where a top view of a radio frequency (RF) powertransistor integrated circuit (IC) device or die 90 is shown. The devicedie and packaging therefore according to the present invention isexpected to have a higher voltage breakdown, improved linearity, betterthermal management, lower R_(dson), higher output impedance, loweroutput capacitance, and extended frequency response when comparedagainst prior art RF power transistors. In an embodiment of the RF powertransistor, die 90 is fabricated from a p-type silicon semiconductor dieor substrate. Various aspects of the inventions described herein findparticular utility in a RF power transistor device that operates atfrequencies greater than 500 MHz and has a power output greater than 5watts. A device operating at these levels must account for bothelectrical and thermal considerations. Moreover, the package and devicebecomes a radio frequency system which marries the electrical andthermal performance in a manner where the device is both rugged andreliable overall operating conditions. Thus, the specification will bedirected to this specific example of an RF power transistor but thoseskilled in the art will appreciate that certain features of thisinvention can be used in other types of semiconductor devices.

The current predominant RF power transistor on the market has a drainand gate of the device wire bonded respectively to the drain and gatelead of the package. The device is a lateral structure having the drainand gate contact on an upper surface of the die and the source contacton the bottom surface of the die. A RF power device typically requiresmore than one wire bond to make a low resistance connection. Multiplewire bonds are used and distributed in a manner that minimizes resistivepath differences to drains of the transistors that comprises the RFpower transistor. In general, the prior art RF power transistor die ismade having a high length to width aspect ratio such that wire bonds aredistributed over the length of the die. The small width of the diereduces the length of the wire bond from the die to the lead of thepackage. A wire bond is an inductor that bandwidth limits the RF powertransistor and is used as an element in an impedance matching network.Wire bond length cannot be perfectly controlled in a productionenvironment and the variance in inductance can impact power amplifieryield. Thus, the preferred embodiment of the present invention employs adesign that eliminates wire bonds.

RF power transistor die 90 has a first major side (top surface) and asecond major side (bottom surface). The first major side of die 90 has afirst electrode interconnection region 58 and a control electrodeinterconnection region 57. In general, first electrode interconnectionregion 58 and control electrode interconnection region 57 are layers ofmetal or metal alloy providing low resistance and excellent thermalconductivity. In an embodiment of the RF power transistor, firstelectrode interconnection region 58 is centrally located on die 90 andprovides an electrically conductive path between source electrodes onthe die and an external metallic contact on the package (which will bediscussed later herein). In general, the RF power transistor comprises anumber of substantially identical transistor cells coupled in parallelto one another. The central active area of die 90 is the area where thetransistor cells of the RF power transistor are formed. In an embodimentof the RF power transistor, first electrode interconnection region 58overlies a majority of the active area and preferably approximately allof the active area. First electrode interconnection region 58 provides alarge contact area, low resistance and substantially equal (balanced)coupling to all transistor cells.

The total area and central location of first electrode interconnectionregion 58 provides a substantial benefit. No wire bonds are required tocouple first electrode interconnection region 58 to the external contactof a RF power transistor package. The metallic external contact or leadof the RF power transistor package can be directly connected to firstelectrode interconnection region 58 eliminating the inductance andresistance of wire bonding. A substantial second benefit of contactingthe surface area of first electrode interconnection region 58 is thatheat can be removed from the first major side of die 90 through the leadof the RF power transistor package. Since first electrodeinterconnection region 58 overlies the active area of die 90, it is alow resistance thermal path in which heat can be effectively pulled outfrom the first major side through the package lead coupled thereto. Byproviding the correct geometry and thermal conductive characteristicsthe lead can also be used as a heat sink or coupled to a heat sink.

A dielectric platform region 20 is formed inside the outer periphery ofdie 90 and outside of the active area. Among other things, dielectricplatform region 20 provides a non-conductive sidewall of dielectricmaterial that extends downward through the epitaxial layer adjacent tothe active transistor cells. In an embodiment of the RF powertransistor, dielectric platform 20 is formed in a ring around the activearea. Among the advantages of the dielectric platform is that it is usedas an edge termination to induce planar breakdown in the active area ofthe transistor thereby increasing the operating voltage of thetransistor. In addition, dielectric platform 20 is used to minimizecapacitance by utilizing the low dielectric constant of platform 20. Inan embodiment of die 90, dielectric platform 20 makes up a substantialportion of the total die area. For example, a dielectric platform couldtake up more than 30-40% of the total die area of a 100 watt RF powertransistor and typically will be greater than 10% of the total die area.Because dielectric platform 20 may constitute a large portion of die 90,it is important that dielectric platform 20 does not induce stress inthe die 90 during wafer processing because it can cause the wafer to bowor warp yielding an unusable wafer. Further details will be providedlater in this description.

Control electrode interconnection region 57 is spaced a predetermineddistance from first electrode interconnection region 58. Typically,control electrode interconnection region 57 does not conduct asubstantial current like first electrode interconnection region 58. Inan embodiment of this invention, control electrode interconnectionregion 57 is shaped as a ring that surrounds first electrodeinterconnection region 58. Control electrode interconnection region 57overlies dielectric platform region 20. The capacitance normallyassociated with control electrode interconnection region 57 is greatlyreduced by isolating it from the underlying semiconductor materialsurface of die 90 thereby increasing frequency and linearity performanceof the RF power transistor.

FIG. 2 is a cross-section of the radio frequency (RF) power transistordie 90 made in accordance with the teachings of this invention. Thepoint of cross-section is indicated by arrow 110 of FIG. 1. A surface ofa p-type substrate 200 is doped forming a heavily doped region or buriedlayer 10. P-type substrate 200 is shown having a substantial portionetched away in this embodiment. Substrate 200 initially isconventionally provided as a wafer having a uniform thickness. In thisembodiment, buried layer 10 is doped N+ and has a low resistance. Asshown, buried layer 10 is continuous and covers the entire surface ofdie 90. An alternate embodiment utilizes a mask to place buried layer 10only in the active area where the transistor cells of the RF powertransistor are formed. For example, buried layer 10 would be masked offfrom being formed around the periphery of die 90 from approximatelydielectric platform region 20 to the edge of die 90.

An epitaxial layer 2 is formed overlying buried layer region 10. In thisembodiment, epitaxial layer 2 is n-type and overlies buried layer 10.Dielectric platform region 20 is formed in epitaxial layer 2 and buriedlayer 10. In this embodiment, dielectric platform region 20 extendsthrough epitaxial layer 2 into (but not through) buried layer 10. Thetop surface of dielectric platform region 20 is approximately planar tothe top surface of epitaxial layer 2. A chemical mechanicalplanarization step can be used to make the surface of dielectricplatform region 20 substantially planar to a surface of epitaxial layer2. Alternately, the top surface of dielectric platform region 20 can beformed using a sequence of wafer processing steps that allows a planarsurface to be formed. As will be described in greater detail herein, thetransistor cells are formed in epitaxial layer 2; thus an active area 30of the device is defined as the area of die 90 corresponding to theportion of epitaxial layer 2 within an inner boundary of the ring shapeof dielectric platform region 20. The dielectric platform thus forms amoat or curtain of insulating material that extends downwardly at leastthrough the epitaxial layer 2 and surrounds the active area 30 of die90. As will be described in detail later herein, the inner sidewall ofthe dielectric platform 20 adjacent to active area 30 is formed as athermal oxide layer such that epitaxial layer 2 (corresponding to activearea 30) terminates on the thermal oxide and provides edge terminationto the transistor. Ideally the sidewall thermal oxide has high integritywith a low level of contaminants therein.

First electrode interconnection region 58 overlies epitaxial layer 2containing active area 30. Control electrode interconnection region 57overlies dielectric platform region 20. As mentioned previously, firstelectrode interconnection region 58 and control electrodeinterconnection region 57 are coupled to metallic contacts or externalleads of a radio frequency package, as will be described herein.

In this embodiment, material is removed from substrate 200 to reduce thethickness of die 90 in the active area 30. A second electrodeinterconnection region 60 is formed on the second or lower major surfaceof die 90. The electrical and thermal path from the second externalcontact of the package to second electrode interconnection region 60 canaffect the performance of the device. In this embodiment, an activeportion of the transistor cell (here, the drain) is electricallyconnected to the external package contact through the epitaxial layer 2and the buried layer 10 that provides a low resistance electrical pathto the second electrode interconnection 60 that, in turn, is connectedto the external package contact 543 (not shown in FIG. 2 but see, forexample FIG. 33). The efficiency of the RF power transistor is relatedto the on-resistance (r_(dson)) of the RF power transistor. Theon-resistance (r_(dson)), in part, related to the resistive path fromepitaxial layer 2 to second electrode interconnection region 60.Similarly, the operating temperature of die 90 and thermally generatednon-linearities are functions of the thermal path from epitaxial layer 2to second electrode interconnection region 60. In general, both thedevice efficiency and thermal performance can be improved by reducingthe thickness of die 90 in particular, in the region of die 90 where thetransistor cells of the RF power transistor are formed in the activearea 30. Heat originates from active area 30 and it is desirable to havedie 90 thinned in this area to reduce the thermal resistance to secondelectrode interconnection region 60 allowing the thermal energy to beremoved through this path. A device having low r_(dson) would bevaluable in applications other than radio frequency power amplifiers.For example, low r_(dson) would be highly desirable in a switchingapplication such as a power management device where the efficiency ofconversion is directly related to the r_(dson) of the transistor.

In this embodiment, material is removed to reduce the thickness from thesecond major surface of die 90 by etching. In general, material fromp-type substrate 200 is removed underlying active area 30. Inparticular, a mask is used to pattern the second major surface of die 90such that an outer peripheral area of the substrate 200 underlyingdielectric platform is not etched. The etch step preferentially removesp-type material from the substrate along a plane in a 54.7 degree angletowards the upper major surface of die 90. N+ buried layer 10 acts as anetch stop in the etching process thereby preventing further materialfrom being removed. As shown, the remaining portion of substrate 200 hasa trapezoidal shaped cross-section that forms a ring around theperiphery of die 90 and is substantially removed from active area 30. Acavity 102 is thus created by the etch step that underlies active area30. Note that the thickness of die 90 in active area 30 is approximatelythe thickness of epitaxial layer 2 and buried layer 10. The remainingportion of substrate 200 formed as a “picture frame” acts to stiffen andsupport die 90. In other words, substrate 200 forms a frame or supportstructure for thinned active area 30 which allows handling of the wafersimilar to a non-thinned wafer. In this embodiment, substrate 200(composed of a high resistivity p-type material) is not ohmicallycoupled to a voltage potential and is substantially left floating.

Buried layer 10 provides a low resistance path for current from theactive area (drain) of die 90 to second electrode interconnection region60. Second electrode interconnection region 60 is formed underlying thesurface of buried layer 10. In an embodiment of the RF power transistor,second electrode interconnection region 60 can be formed from a metal ormetal alloy for low resistance and excellent thermal conductivity. Theshape of the lower major surface of die 90 provides another substantialbenefit. The external metal contact or lead of the RF package can bedesigned to fit in cavity 102. The lead is then easily aligned andcoupled to second electrode interconnection region 60. For example, thelead can be physically and electrically coupled to second electrodeinterconnection region 60 by solder or a conductive epoxy. The lead canthen be used to handle die 90 in subsequent steps to package the device.Directly coupling the lead to second electrode interconnection region 60minimizes inductance and provides a large surface area for removing heatthrough the lower major surface of die 90. Thus, the thermal efficiencyis substantially greater than prior art RF power transistors becauseheat can be removed from both the first (upper) and second (lower) majorsurfaces simultaneously. Moreover, the increased thermal efficiency isachieved while improving device performance by reducing parasitics thatdegrade device operation.

There are alternate embodiments that result in a device of reducedthickness although some may lack some of the benefits describedhereinabove. For example, a substrate comprising N+ material could beused. Buried layer 10 would not be needed with a N+ substrate. The N+substrate could be thinned using wafer grinding/thinning techniques wellknown to one skilled in the art. A second electrode interconnectionregion would then be formed overlying the thinned N+ substrate. The diewould have a uniform thickness in this embodiment.

FIGS. 3-21 are exploded cross-sectional views of a portion of the RFpower transistor of FIG. 2 that sequentially illustrate wafer processingsteps to form the device in accordance with an embodiment of the presentinvention. In most cases, different reference numbers are used for thesame items as in FIGS. 1-2. FIG. 3 is an enlarged cross-section of anarea of the RF power transistor near a periphery of the die 90.Illustrating the die periphery allows the fabrication of the dielectricplatform 20, edge termination, and a transistor cell to be shown.However, it should be understood that the RF power transistor device ofthe preferred embodiment includes a number of these transistor cellscoupled in parallel to form an array of mesh-connected transistor cells.Moreover, the values given in this description of the invention are forillustrative purposes. It is well known that the design of RF powertransistors vary greatly depending on the specific desired operatingcharacteristics of the device such as power and frequency and that thesevariations fall under the scope of this description.

The processing steps shown in FIGS. 3-21 are applied to a first majorsurface of the die (sometimes referred to herein as the upper surface).The second major surface of the die (sometimes referred to as the lowersurface) is protected during wafer processing on the first majorsurface. For example, an oxide layer is formed on the second majorsurface. A layer of silicon nitride is then formed over the oxide layer.The combination of the oxide layer and the silicon nitride layer willprotect the second major surface during wafer processing on the firstmajor surface. Additional protective layers can be added should theprotective layers on the second major surface be removed during any ofthe wafer processing steps. The subsequent etching step to create thecavity in the second major surface of the die and forming the secondelectrode interconnection region are not shown in FIGS. 3-21 but werepreviously described in connection with FIG. 2

A starting material for forming the RF power transistor device of thepresent invention comprises a substrate 200. In an embodiment of thewafer process, substrate 200 is a p-type silicon substrate having acrystal orientation. Buried layer 205 is formed in substrate 200 andtypically is a highly doped low resistance layer. In an embodiment ofthe wafer process, buried layer 205 is doped N+ and is approximately 15μm thick. Buried layer 205 has a resistivity in a range of 0.001 Ω-cm to0.02 Ω-cm and is provided to improve ohmic contact to a second electrodeinterconnection region. Buried layer 205 is exposed by etching awaysubstrate 200 in a subsequent step (not shown) to allow the secondelectrode interconnection region to be formed thereon.

Epitaxial layer 210 overlies buried layer 205. In an embodiment of thewafer process, epitaxial layer 210 is n-type. Initially, epitaxial layer210 is approximately 25 μm. Subsequent thermal processes will change theresistivity and the thickness of this region to approximately 20 μmwhich is selected for determining a breakdown voltage of the RF powertransistor. In particular, epitaxial layer 210 has been selected tosupport 25V/μ, thus allowing a RF power transistor with a 500 Vbreakdown voltage to be created.

It is highly desirable for power efficiency to operate a RF powertransistor at as high a voltage as possible. Prior art silicon RF powertransistors operating at approximately 2 GHz are design limited for highvoltage operation. For example, the standard for power amplifieroperating voltage is 28 volts for a cellular base transceiver station(BTS) power amplifier (PA). A general rule of thumb for RF powertransistor breakdown voltage to operating voltage is approximately 3to 1. In other words the breakdown voltage for state of the art RF powertransistors is approximately 75 volts. The 28 volt power amplifieroperating voltage yields disappointing power efficiency ratings in the25% range. A RF power transistor operating at a voltage greater than 28volts will operate at a lower current to generate the same power output.Operating at lower current in conjunction with a low r_(dson) results inimproved device efficiency. Moreover, the lower operating currentreduces the thermal requirements on the device which increasesreliability. The output impedance of the transistor also increases withoperating voltage. Higher output impedance allows a more efficientmatching network to be designed for the power amplifier. Thus, a RFpower transistor with a higher voltage breakdown has a substantialadvantage. For example, the RF power transistor of this invention havinga 500 V breakdown voltage can operate at supply voltages greater than150 V which will significantly increase the power efficiency. Similarly,a RF power transistor manufactured as disclosed herein with a 150Vbreakdown voltage that is operated at 50 V would have a substantialadvantage over the existing 28 V transistors.

A dielectric layer 215 overlies epitaxial layer 210. In an embodiment ofthe wafer process, dielectric layer 215 comprises SiO₂. The layer ofSiO₂ is thermally grown overlying epitaxial layer 210 having a thicknessof approximately 5000 Å. A masking layer 220 is formed overlyingdielectric layer 215. Masking layer 220 is patterned exposing portionsof dielectric layer 215. The exposed portions of dielectric layer 215are removed revealing the underlying epitaxial layer 210. Masking layer220 is then removed. An etching process is then performed to form amatrix of hexagonal vertical hollow wells or cavities 225 in a ringsurrounding the active area in the manner illustrated at 57 in FIG. 1.In particular, an anisotropic etching process is used to etchsubstantially vertically through at least the epitaxial layer 210 and,preferably, at least part way into buried layer 205. In this embodiment,vertical cavities 225 are approximately 2.0 μm wide and spaced 0.4 μmapart from one another and define a matrix of vertically extendingstructures or walls. Using the anisotropic etching process, verticalcavities 225 are etched through epitaxial layer 210 and into buriedlayer 205 to a depth of approximately 30 μm deep. The etching ofvertical cavities 225 creates silicon matrix walls 230 between thecavities 225. The innermost wall 230 a spans outer portions of epitaxiallayer 210 and buried layer 205 in the active area. Silicon matrix walls230 are approximately 0.4 μm wide. Dielectric layer 215 is affected bythe above wafer process steps such that dielectric layer 215 is reducedin thickness from the SiO₂ layer of 5000 Å to approximately 3000 Å.

Referring to FIG. 4, an optional process step is illustrated thatremoves material from silicon matrix walls 230. A silicon etch isperformed that etches exposed portions of silicon matrix walls 230,epitaxial layer 210, and buried layer 205. In an embodiment of the waferprocess, the silicon etch thins silicon matrix walls 230 to a width orthickness of approximately 0.2 μm.

Referring to FIG. 5, a thermal oxidation process is performed that formssilicon dioxide on any exposed silicon area. In particular, the siliconof silicon matrix walls 230 of FIG. 4 are substantially completelyconverted to silicon dioxide forming silicon dioxide matrix walls 235 inthe form of a matrix of vertically extending dielectric structures. Theexposed silicon surface of the innermost wall (230 a in FIG. 4), thebottom of cavities 225 (240 in FIG. 4) and the outermost wall (230 b inFIG. 4) are likewise converted to thermal oxide layers 235 a, 241 and235 b as shown in FIG. 5. The thermal oxide layer 235 a adjacent to theactive area where the transistor cells are formed is an edge terminationto induce planar breakdown in the RF power transistor. Depending on theapplication, it may be desirable to deposit further dielectric materialto increase the thickness of the dielectric material to enhance avoltage that can be withstood before breakdown occurs. A furtherconsideration is the time required to form the dielectric layer andstress applied to the structure. For example, an additional depositionof a polysilicon layer is performed. Then, a thermal oxidation stepoxidizes the polysilicon layer forming dielectric layer 260 thatincreases the amount of dielectric material on silicon dioxide matrixwalls 235, 235 a, 235 b and 241.

Referring to FIG. 6, a dielectric material is applied to the die. In anembodiment of the wafer process, a low-pressure deposition of TEOS(tetra-ethyl-ortho-silicate) 245 is applied to the first major surface.Some of the deposited material builds up in each opening of verticalcavities 225 gradually reducing the size of the opening until theopening is closed forming a dielectric plug or layer 246. The remaininglower portions of cavities 225 are not filled in this embodiment. In analternate embodiment, the lower portions of the cavities could be filledwith a dielectric material if so desired. Note that a continuous layerof dielectric material is formed in each cavity 225 by way of dielectriclayer 245, dielectric matrix walls 235, and dielectric layer 260. Thislayer of dielectric material is denoted as dielectric platform 255. Inan embodiment of the wafer process, approximately 11,000 Å of TEOS isdeposited such that an upper region of vertical cavities 225 are sealed.A thermal oxidation process follows that densifies the TEOS that is partof dielectric platform 255.

In one embodiment, an oxide CMP (chemical mechanical planarization) stepis then performed to planarize the oxide on the first major surfaceafter the dielectric material deposition. The CMP step removes from thefirst major surface portions of TEOS layer 245 and dielectric layer 260and creates a planar surface 250 on the first major surface of the die.It should be noted that although vertical cavities 225 are sealed at theupper surface by dielectric layer 245, vertical cavities 225 are notfilled with solid material and comprise a substantial amount of emptyspace. A protective layer 265 is then applied overlying the oxide on thefirst major surface. In an embodiment of the wafer process, a layer ofsilicon nitride approximately 500 Å thick overlies planar surface 250.As mentioned previously, an alternate process flow that does not requirean oxide CMP step could be developed should CMP not be available. Thesurface should be sufficiently planar to prevent step coverage problemswith subsequent wafer processing steps.

In general, dielectric platform 255 is formed greater than 10 micronswide and 4 microns deep. The control electrode interconnection region 57(FIGS. 1-2) is formed overlying dielectric platform 255 and is formedgreater than 10 microns wide to ensure low resistance. In an embodimentof the RF power transistor, dielectric platform 255 is formed to a depthgreater than 4 microns to standoff a voltage required of deviceoperation and to reduce gate to drain capacitance from the controlelectrode interconnection region. Moreover, dielectric platform 255 canbe formed at these dimensions or greater without significant stressbeing added to the die. Also, it should be understood that variousdifferent manufacturing processes can be employed to form the dielectricplatform. For example, the cavities can be filled forming a soliddielectric platform.

For high voltage applications, dielectric layer 245 by itself may not besufficient to stand off the desired voltage. As mentioned previously, anoptional dielectric layer 260 was added to the bottom and sidewalls thatdefine vertical cavities 225. In an embodiment of the wafer process forforming a 500V breakdown RF power transistor, prior to formingdielectric layer 245, polysilicon is deposited into vertical cavities225 forming a polysilicon layer on the bottom and sidewalls. Forexample, 1000 Å of polysilicon is deposited into vertical cavities 225.The polysilicon is then oxidized to form a 2200A oxide layer in verticalcavities 225. A second, 1000 Å of polysilicon is then deposited andoxidized to form a second 2200 Å oxide layer in vertical cavities 225.The combination forms a 4400 Å oxide layer in vertical cavities 225 thatis denoted as dielectric layer 260. Dielectric layer 260 is formed inmore than one step to reduce the oxidation time. Other techniques knownto one skilled in the art can also be applied that increase the amountof dielectric material. The openings to vertical cavities 225 cannot bemade so large that they cannot be closed by a process step such as thelow pressure TEOS deposition.

In general, the dielectric platform is a non-conductive structure havinga low dielectric constant that provides edge termination for thevertical RF power transistor to improve breakdown voltage. Thedielectric platform must be capable of standing off the breakdownvoltage of the transistor. For example, the total oxide thickness on thebottom 241 of cavities 225 of dielectric platform 255 (or the sidewall235 a adjacent to the active area of the RF power transistor) incombination with dielectric layer 245 is designed to withstand 500volts. From a structural perspective, the oxide formed on the bottom 241of cavities 225 and the sidewall 235 a adjacent to the active areashould not be formed to a thickness where stress is induced intosubstrate 200 that produces warpage in the wafer. Thus, the dielectricplatform is designed to withstand the breakdown voltage of the RF powertransistor while minimizing stress imparted to the wafer when thedielectric platform comprises a substantial portion of the die area.

Edge termination comprises a sidewall formed of a dielectric materialadjacent to the active area of the transistor which aids in achievingplanar breakdown within the structure. In an embodiment of thetransistor, the active area is bounded by dielectric platform 255 suchthat the drain region (epitaxial layer 210) of the transistor terminatesin a thermal oxide sidewall of dielectric platform 255. Ideally, thesidewalls of a dielectric platform are formed to terminate electricfields in the drain region of a RF power transistor at a 90 degree angleto minimize field curvature. Thus, an equipotential electric field linein the drain of the transistor would be approximately horizontal inepitaxial layer 210. Electric field lines of different potential wouldbe in different horizontal planes but parallel to one another withinepitaxial layer 210. Care should be taken in forming the thermal oxidesidewall to prevent trapped charge that could add curvature to theelectric field and lower transistor breakdown voltage.

The dielectric platform 255 is also a support structure that requiressufficient structural strength to allow the formation of interconnect,passive components, or active devices overlying the platform. Ingeneral, vertical support structures are formed that support a topsurface layer. The vertical support structures and top surface layercomprise a dielectric material. In one embodiment, empty compartmentsunderlying the top surface layer are formed between the vertical supportstructures to form air gaps that lower the dielectric constant of thedielectric platform. Conversely, a solid or filled dielectric platformcould be formed which would have a higher dielectric constant ifdesired. In the embodiment shown, dielectric platform 255 is an array ofhexagonal cells having vertical walls formed of silicon dioxide whenviewed looking down on the top surface. The center region of eachhexagonal cell is an empty void or space. A cap or top surface layer isformed to seal each hexagonal cell. The diameter of a cell in dielectricplatform 255 is determined by the capping process. The diameter of thecell is selected to allow the build up of deposited dielectric materialnear the opening near the top surface which closes off and seals thecell without filling the cell up (with the deposited dielectric materialsuch as TEOS). Similar spacing constraints would apply to other air gapdielectric platforms requiring a capping process.

The dielectric platform 255 also reduces parasitic capacitances of a RFpower transistor thereby extending the frequency response of the device.The dielectric platform separates conductive regions from one anotherthus a low dielectric constant is preferred to minimize the capacitance.The lowest dielectric constant for a dielectric platform is achieved bymaximizing the volume of empty space in the platform between conductiveregions which form the parasitic capacitance. In particular, the numberof cells in dielectric platform 255 or the area of the die thatdielectric platform 255 comprises is related to reducing the gate todrain and drain to source capacitance which will be described in moredetail herein below.

Referring to FIG. 7, a mask layer 270 is applied and patterned on thefirst major surface. Mask layer 270 overlies dielectric platform 255.Exposed portions of protective layer 265 are removed revealing theunderlying oxide layer 215. In an embodiment of the wafer process, oxidelayer 215 of FIG. 6 is reduced in thickness to approximately 100 Å. Anoptional layer 275 is formed that is more heavily doped than epitaxiallayer 210 to reduce the R_(DSon) of the RF power transistor. In anembodiment of the process, layer 275 is doped with an arsenic orphosphorous ion implantation process. Oxide layer 215 is removed and anew oxide layer 280 is formed overlying layer 275. In an embodiment ofthe wafer process, oxide layer is thermally grown to a thickness in arange of 200 Å to 1000 Å and preferably 700 Å.

Referring to FIG. 8, a protective layer 285 is formed overlying thefirst major surface. In an embodiment of the wafer process, protectivelayer 285 is a silicon nitride layer (Si₃N₄). The silicon nitride layeris formed having a thickness of approximately 500 Å. Protective layers265 and 285 in the exemplary embodiment are both silicon nitride layershaving a combined thickness of approximately 1000 Å overlying dielectricplatform 255.

A masking layer (not shown) is provided and patterned overlying thefirst major surface. The pattern exposes an opening 290 that is inboardand adjacent to dielectric platform 255. In opening 290, protectivelayer 285 is removed revealing underlying dielectric layer 280.Dielectric layer 280 is then removed in opening 290 exposing layer 275.A polysilicon layer 295 is then deposited overlying the first majorsurface. Polysilicon layer 295 couples to exposed layer 275 in opening290. In an embodiment of the wafer process, polysilicon layer 295 isformed having a thickness of approximately 250 Å.

A layer 300 is then formed overlying the first major surface. Layer 300is a conductive material. In an embodiment of the wafer process, layer300 is a tungsten silicide layer (WSi_(2.8)). The tungsten silicidelayer is formed having a thickness of approximately 500 Å. A polysiliconlayer 305 is then formed overlying the first major surface. In anembodiment of the wafer process, polysilicon layer 305 is formed havinga thickness of approximately 250 Å. A pre-implant silicon dioxide layerapproximately 100 Å thick is then formed. A p-type region 310 is formedby a blanket implantation process which dopes through opening 290.Protective layer 285 prevents doping in other areas of the top surface.The blanket implantation process also dopes polysilicon layers 295 and305, and tungsten silicide layer 300. In an embodiment of the waferprocess, the dopant is boron and it is implanted at approximately 5 KeV.Tungsten silicide (WSi_(2.8)) is used to form layer 300 for filmstability consideration. The tungsten silicide layer 300 and dopedpolysilicon layers 295 and 305 serve as a grounded shielding plate thatsignificantly reduces gate to drain capacitance of the RF powertransistor. Reduction of the gate to drain capacitance greatly extendsthe operating frequency of the device. Although multiple conductivelayers are disclosed that couple in common to form a composite lowresistance grounded shielding plate layer it should be understood that asingle conductive layer could also be used if desired. The composite lowresistance grounded shielded plate layer is coupled to ground throughp-type doped region 310 which is described in more detail herein below.

Referring to FIG. 9, a masking layer (not shown) is formed and patternedover the first major surface. The patterned masking layer has an opening315 over dielectric platform 255. Polysilicon layer 305, tungstensilicide layer 300, and polysilicon layer 295 are removed in opening 315revealing protective layer 285. The remaining masking layer is thenremoved and a protective layer 320 is formed overlying the first majorsurface. In an embodiment of the wafer process, protective layer 320comprises silicon nitride (Si₃N₄). The silicon nitride is formedapproximately 500 Å thick over the first major surface.

A dielectric layer 325 is then formed over the first major surface. Inan embodiment of the wafer process, dielectric layer 325 comprises TEOS(tetra-ethyl-ortho-silicate). The TEOS dielectric layer is approximately4000 Å thick. Although more than one non-conductive layer (layers 320,325) is disclosed hereinabove that form an isolation region betweenconductive layers of the transistor it should be understood that asingle non-conductive layer could also be used if desired.

A polysilicon layer 330 is then formed overlying the first majorsurface. In an embodiment of the wafer process, polysilicon layer 330 isn-doped polysilicon. The n-doped polysilicon layer is approximately 500Å thick. A layer 335 is then formed overlying the first major surface.In an embodiment of the wafer process, layer 335 is a conductive layercomprising tungsten silicide (WSi_(2.8)). The tungsten silicide layer isformed approximately 3000 Å thick. The layer 335 is provided to reducegate resistance and could alternatively be constructed of dopedpolysilicon or tungsten. Some of the steps provided hereinabove arethermal steps that drive in edge termination region 310 such that it isdiffused into epitaxial layer 210 extending below layer 275. Apolysilicon layer 340 is then formed overlying the first major surface.In an embodiment of the wafer process, polysilicon layer 340 is n-dopedpolysilicon. The n-doped polysilicon layer is formed approximately 500 Åthick. Although multiple conductive layers (layers 330, 335, and 340)are disclosed that couple in common to form a composite low resistancelayer it should be understood that a single conductive layer could alsobe used if desired.

A thermal oxidation process is then performed that oxidizes an upperportion of polysilicon layer 340. In an embodiment of the wafer process,a dielectric layer 345 is formed in the thermal oxidation process. Thethermal oxidation process forms an oxide layer approximately 150 Å thickfrom polysilicon layer 340. A protective layer 350 is then formedoverlying the first major surface. In an embodiment of the waferprocess, protective layer 350 comprises silicon nitride (Si₃N₄). Thesilicon nitride is formed approximately 1500 Å thick. Although more thanone non-conductive layer (layers 345, 350) is disclosed hereinabove itshould be understood that a single non-conductive layer could also beused if desired

Referring to FIG. 10, a masking layer (not shown) is formed andpatterned overlying the first major surface. The pattern in the maskinglayer includes an opening 355 exposing protective layer 350. The opening355 corresponds to an area of the die where a single transistor cell ofthe RF power transistor is formed. Although not shown in this figure, itshould be noted that the RF power transistor will comprise a pluralityof transistor cells formed within the active area of the die. Thefollowing layers are removed in opening 355: protective layer 350,dielectric layer 345, polysilicon layer 340, tungsten silicide layer335, polysilicon layer 330, dielectric layer 325, protective layer 320,polysilicon layer 305, tungsten silicide layer 300, and polysiliconlayer 295, thus stopping on protective layer 265. The masking layer isthen removed.

A protective layer is then formed overlying the first major surface. Inan embodiment of the wafer process, the protective layer comprisessilicon nitride. The silicon nitride layer is formed approximately 500 Åsuch that it overlies protective layers 350 and 265 (both siliconnitride in the exemplary embodiment). In particular, the protectivelayer is conformal and forms on the sidewalls of opening 355. Theprotective layer on the sidewalls is indicated as protective layer 365.

In an embodiment of the wafer process, an anisotropic etch is used toremove some of the upper portion of protective layers 350 and 265. Inparticular, material is removed from the upper portion of protectivelayers 350 leaving protective layer 365 on the sidewalls of opening 355.Because protective layer 350 is substantially thicker than protectivelayer 265, a portion of protective layer 350 remains following the etchprocess while protective layer 265 in opening 355 is removed. Removingprotective layer 265 in opening 355 exposes an underlying dielectriclayer. This dielectric layer is then removed revealing layer 275. A gateoxide layer 360 is thermally grown to a thickness of 25 Å to 150 Å. Athicker gate oxide could be used if a higher gate to source breakdownvoltage was desired. In particular, gate oxide layer 360 is formedapproximately 100 Å thick. A polysilicon layer 370 is then formedoverlying the first major surface. In an embodiment of the waferprocess, polysilicon layer is undoped polysilicon. The undopedpolysilicon layer is formed approximately 1000 Å thick.

Referring to FIG. 11 a thermal oxidation process is performed thatoxidizes a portion of polysilicon layer 370. The oxidation process formsa dielectric layer 375. In an embodiment of the wafer process,dielectric layer 375 is formed approximately 150 Å thick. An implantstep is then performed. In an embodiment of the wafer process, boron isimplanted in quadrature at three different energies. In particular, someof the p-dopant is provided into layer 275 through opening 355 atdifferent depths corresponding to the different energy used in theimplant. Using more than one implant and implant energy allows controlof the doping profile. For example, the implants control the thresholdvoltage of the device or when device punch through occurs. Thus, ap-doped region 380 is formed. Doped region 380 is formed havingapproximately the same depth as layer 275 and couples to p-doped region310. A protective layer 385 is then formed overlying the first majorsurface. In an embodiment of the wafer process, protective layer 385comprises silicon nitride (Si₃N₄). The silicon nitride layer is formedapproximately 250 Å thick.

Referring to FIG. 12 a dielectric layer is formed overlying the firstmajor surface. In an embodiment of the wafer process, the dielectriclayer comprises TEOS. The TEOS layer is formed approximately 3500 Åthick. The dielectric layer is then anisotropically etched revealingportions of protective layer 385. The anisotropic etch leaves adielectric region 390 on the sidewalls in opening 355. Dielectric region390 acts as a mask for protective layer 385 on the sidewall and aportion of the floor of opening 355. Exposed portions of protectivelayer 385 are then removed revealing underlying dielectric layer 375. Asidewall spacer is thus formed comprising protective layer 385 anddielectric region 390.

Referring to FIG. 13, exposed portions of dielectric layer 375 areremoved revealing underlying polysilicon layer 370. Dielectric region390 is also removed in this wafer process step. Dielectric layer 375underlying protective layer 385 remains. Exposed portions of polysiliconlayer 370 are then removed revealing protective layer 350. An opening395 is formed by removing polysilicon layer 370 revealing underlyinggate oxide layer 360. Gate oxide layer 360 in opening 395 is thenremoved revealing doped region 380. A sidewall spacer remains comprisingpolysilicon layer 370, dielectric layer 375, and protective layer 385.

Referring to FIG. 14, protective layers 350 and 385 are removed.Removing protective layer 350 reveals underlying dielectric layer 345.Removing protective layer 385 reveals underlying dielectric layer 375.Dielectric layer 375 is then removed revealing underlying polysiliconlayer 370. A dielectric layer 400 is formed in opening 395 on dopedregion 380. In an embodiment of the wafer process, dielectric layer 400is a thin pre-implant thermal oxide. An implant step is then performedforming a doped region 405. In an embodiment of the wafer process, thedopant is arsenic (n-type). In particular, the implant dopes polysiliconlayer 370 and is implanted through opening 395 into doped region 380 toform doped region 405 which relates to a source of the transistor cell.In an embodiment of the device to ensure adequate coverage, the ionimplantation is performed at an angle of approximately 45°, inquadrature, such that the polysilicon layer 370 is converted to N typeduring the wafer process step.

Referring to FIG. 15, dielectric layer 400 is removed from the firstmajor surface. A polysilicon layer 410 is then formed overlying thefirst major surface. In an embodiment of the wafer process, thepolysilicon is undoped polysilicon. The undoped polysilicon is formedapproximately 1500 Å thick. A thermal oxidation step is then performedthat forms a dielectric layer 415 by oxidizing a portion of polysiliconlayer 410. In an embodiment of the wafer process, the thermal oxidationstep forms dielectric layer 415 approximately 50 Å thick.

A protective layer is then formed overlying the first major surface. Inan embodiment of the wafer process, the protective layer comprisessilicon nitride (Si₃N₄). The silicon nitride layer is formedapproximately 1500 Å thick. An anisotropic etch is performed on theprotective layer leaving a sidewall spacer 420. A thermal oxidationprocess is then performed that oxidizes exposed portions of polysiliconlayer 410. A dielectric layer 425 is formed by the thermal oxidationprocess. In an embodiment of the wafer process, dielectric layer 425 isformed approximately 300-400 Å thick. The thermal process convertspolysilicon layer 410 from undoped polysilicon to n-type polysilicon.Although not shown, the thermal process also forms a thin layer(approximately 20 Å of oxide) on sidewall spacer 420.

Referring to FIG. 16, sidewall spacer 420 of FIG. 15 is removedrevealing underlying dielectric layer 415 of FIG. 15. The exposedportion of dielectric layer 415 is then removed. Dielectric layer 415 isthinner than dielectric layer 425 and thus can be removed while stillleaving some of dielectric layer 425 intact. An anisotropic etch is thenperformed on an exposed portion of polysilicon layer 410.Anisotropically etching the exposed portion of polysilicon layer 410forms opening 430 and reveals underlying gate oxide layer 360.

A thin pre-implant oxide layer is formed in opening 430. An implant stepis performed to provide dopant through opening 430 into doped region380. The implant forms a doped region 435. In an embodiment of the waferprocess, an n-type dopant is used such as arsenic or phosphorus. Then-type dopant ion implantation is performed at 7° in quadrature having aconcentration in the range of 1E14-1E16 to ensure good coverage. In anembodiment of the transistor a doping concentration of 5E14 is used inn-type doped region 435. Doped region 435 defines the edge of the sourceregion that is adjacent to the channel region of the transistor cell.The thermal processes performed hereinabove causes doped region 405 tofurther diffuse, both vertically and horizontally, into doped region380.

Referring to FIG. 17, a protective layer 440 is formed overlying thefirst major surface. In an embodiment of the wafer process, protectivelayer 440 comprises a silicon nitride layer (Si₃N₄). The silicon nitridelayer is formed approximately 250 Å thick. A polysilicon layer is thenformed overlying the first major surface. In an embodiment of the waferprocess, the polysilicon layer comprises an undoped polysilicon layer.The undoped polysilicon layer is formed approximately 4000 Å thick. Ananisotropic etch is performed on the polysilicon revealing portions ofprotective layer 440. The anisotropic etch leaves a portion of thepolysilicon layer that is denoted as sidewall region 445.

A dielectric layer (not shown) is formed over the first major surface.In an embodiment of the wafer process, the dielectric layer comprisesTEOS. The TEOS layer is formed approximately 150 Å thick. An implantstep is then performed. In an embodiment of the wafer process, a boronimplant having a concentration between 1E14 to 1E15 and moreparticularly a concentration of 2E14 is implanted. The implant is selfaligning through opening 450 and penetrates through protective layer 440and polysilicon layer 410 into doped region 380. A doped region 455 isformed by the implant that extends into doped region 380. The implantforms an enhanced p-type layer that is more lightly doped than the dopedregion 405 through which it was implanted. Doped region 455 reducesvertical gain of the parasitic bipolar transistor that is part of the RFpower transistor structure.

Referring to FIG. 18, the dielectric layer formed in FIG. 17 is removed.Sidewall region 445 is then removed revealing protective layer 440. Aprotective layer is then formed over the first major surface. In anembodiment of the wafer process, the protective layer is silicon nitride(Si₃N₄). The silicon nitride layer is then formed approximately 750 Åthick. The combination of the silicon nitride layer and protective layer440 is denoted by protective layer 460. A dielectric layer 465 is thenformed over the first major surface. In an embodiment of the waferprocess, dielectric layer 465 comprises TEOS. The TEOS layer is formedapproximately 6000 Å thick. The TEOS is densified in a thermal processat a temperature of approximately 700° C. The densification step isfollowed by a rapid thermal anneal process. These processes causeregions 405 and 435 of FIGS. 16-17 to combine to form region 437. Region437 corresponds to the source of the transistor cell. The thermal annealactivates edge termination region 310, doped region 380, doped region437, doped region 455, and optional doped region 275 and sets thejunction profiles. Region 310 and region 380 are both p-type andelectrically coupled together. It should be noted that the sequence ofwafer processing steps provides substantial benefits from a thermalperspective. For example, dielectric platform 255 is formed before thetransistor cells in the active area thus the high temperature stepsrequired to oxidize large areas of the die are performed before implantsare made. Similarly, the majority of the dopings in the active area ofthe transistor are activated near the end of the process flow whichallows the implants to be placed without moving substantially due toadditional thermal steps that plague other transistor designs. Thisproduces a device that can be manufactured consistently with low processvariation and higher device performance.

Referring to FIG. 19, a masking layer is formed and patterned overlyingthe first major surface. An opening 470 is exposed by the patternedmasking layer and corresponds to a control electrode interconnectionregion that couples to the control electrode of each transistor cell ofthe RF power transistor. As shown, only part of opening 470 isillustrated. Opening 470 corresponds to control electrodeinterconnection region 57 of FIG. 1. In opening 470, the followinglayers are removed: dielectric layer 465, protective layer 460,dielectric layer 425, polysilicon layer 410, dielectric layer 345,polysilicon layer 340, tungsten silicide layer 335, polysilicon layer330, and partially dielectric layer 325. In an embodiment of the waferprocess, opening 470 is etched approximately 1000 Å into the TEOS layercorresponding to the exemplary embodiment of dielectric layer 325. Theremaining masking layer is then removed.

A masking layer is then formed and patterned overlying the first majorsurface. An opening 475 is exposed by the patterned masking layer andcorresponds to a first electrode interconnection region that couples tothe first electrode of each transistor cell of the RF power transistor.The first electrode interconnection region corresponds to the firstelectrode interconnection region 58 of FIG. 1. In this embodiment, thereis an array of mesh connected MOS transistor cells that are connected inparallel to form the RF power integrated circuit device of thisinvention. As will be explained, all of the gates of the transistorcells are connected via conductive pathways to the interconnectionregion 57 which, in turn, is mated with an external metallic contact ofthe package. In opening 475, the following layers are removed,dielectric layer 465, protective layer 460, and polysilicon layer 410.An etch step is performed that etches through doped region 437. Materialis removed such that opening 475 extends into doped region 455.

Referring to FIG. 20, the remaining masking layer is removed. A thindiffusion barrier material 480 is formed overlying the first majorsurface. In an embodiment of the wafer process, barrier material 480comprises a material such as titanium and titanium nitride (Ti—TiN). Aconductive layer is then formed overlying the first major surface. In anembodiment of the wafer process, a low electrical and thermal resistancematerial is used for the conductive layer, for example gold. In anembodiment of the wafer process, the gold layer is formed have athickness of approximately 1 μm to 3 μm. Other metals or metal alloysknown to one skilled in the art could also be used instead of gold.

A masking layer is formed and patterned overlying the first majorsurface. An opening 485 is formed through the conductive layer andbarrier material 480 to separate a control electrode interconnectionregion 490 (corresponding to item 57 in FIGS. 1-2) from a firstelectrode interconnection region 495 (corresponding to item 58 in FIGS.1-2). In an embodiment of the wafer process, opening 485 is between 10μm and 50 μm in width.

Referring to FIG. 21 is a cross-section of a portion of a RF powertransistor in accordance with the present invention. Similar to FIG. 2,the RF power transistor is etched or thinned to reduce a thermalresistance of the device. In an embodiment, of the RF power transistor,an exposed surface of substrate 200 is masked exposing substrate 200corresponding to the active area of the transistor. An etch process isperformed on the exposed p-type material of substrate 200 that stops onthe n-type buried layer 205 forming a cavity region 500. Thus, the diethickness in the region where current is conducted by the RF powertransistor is approximately the thickness of epitaxial layer 210 andburied layer 205 making the thermal resistance and the on-resistance ofthe transistor very low.

In an embodiment of the RF power transistor, substrate 200 forms asupport structure or frame at the periphery of the die. A metal layer isformed on buried layer 205 exposed after the etching process. The metallayer forms a second electrode interconnection region 510 that iselectrically coupled to buried layer 205. Thus, first electrodeinterconnection region 495 and control electrode interconnection region490 can be coupled to external contacts of a package from the top sideof the die similar to that shown in FIG. 1 while second electrodeinterconnection region 510 can be coupled from a bottom side of the dieto an external package contact. How contact is made from the first,control, and second electrodes to the package leads will be described indetail herein below.

As mentioned previously, a portion of the RF power transistor is shownin FIG. 21 near a periphery of the die to illustrate features of thedevice. Although only a single transistor cell is shown, the RF powertransistor comprises a plurality of transistor cells coupled in parallelin the active area of the device. Transistor cells adjacent to thedielectric platform may differ from transistor cells (not shown)interior to the active area by p-type region 310. In general, atransistor cell has a channel that is contiguous around the sourceregion. Thus, current conduction through the channel occurs in alldirections away from the source region into the drain region (epitaxiallayer 210). The transistor cell shown in FIG. 21 is prevented fromconducting on the side where p-type region 310 resides because aconductive path to the drain region does not exist (epitaxial layer210). The transistor cell conducts in all other directions where thechannel couples to n-type layer 275.

Each transistor cell of the RF power transistor is a MOSFET structurehaving a gate region, source region and drain region. The RF powertransistor has a common drain since epitaxial layer 210 is common toeach drain of each transistor cell. Thus, the transistor cell drainscannot be decoupled from one another. The common drain (epitaxial layer210) is coupled to buried layer 205 and second drain electrodeinterconnection 510 (60). The gates of each transistor cell are coupledtogether via a low resistance interconnect stack. For example, layers330, 335, and 410 comprise a low resistance interconnect layer thatcouples to the gate of each transistor cell thereby coupling them incommon. Layers 330, 335, and 410 couple to control electrodeinterconnection 490 (57). Similarly, the source of each transistor cellis coupled in common by first electrode interconnection region 495 (58).First electrode interconnection region 495, control electrodeinterconnection region 490, and second electrode interconnection region510 respectively couple to the source, gate, and drain leads of thepackage.

In an embodiment of the RF power device the gate length of eachtransistor cell is determined non-photolithographically. The gateelectrode of the transistor cell comprises polysilicon layer 370 andpolysilicon 410. Polysilicon layer 370 overlies a thin gate oxide 360(FIG. 16) formed over p-type region 380. Underlying the gate oxide isthe channel region of the transistor cell. Forming the gate in thismanner has advantages. The deposition of material such as polysiliconcan be controlled with great accuracy in a wafer fabrication facility(wafer fab). The gate length is determined by the combined widths ofpolysilicon layers 370 and 410, i.e., the thickness of layer 370 and thethickness of deposited polysilicon layer 410. What this means is that atransistor can be produced with a state of the art gate length (ex.0.2-0.3 microns or lower) in a wafer fab having photolithographiccapabilities greater than 0.35 microns. The short channel length of thetransistor results in high gain, low on-resistance, and extendedfrequency response. In particular, high gain that results in a widerfrequency power gain curve is a result of the transistor cell design.The RF power device can be built at much lower cost since productioncost is directly related to the photolithographic capability of thewafer fab. Moreover, tighter control over gate lengths can be achievedwith lower variance because of the control wafer processing facilitieshave over material deposition thicknesses (such as polysilicon).

The RF power transistor and package is an electrical and thermal system.These devices have very stringent requirements that must be met forcommunication applications. In particular, a RF transistor has to becapable of operating under a full power condition for a period of noless than 34 years mean time to failure to meet the specification foruse in a cellular base transceiver station power amplifier. Heat removalis one of the limiting factors in providing a reliable high power RFtransistor. For example, it has been found that a silicon transistoroperated at a junction temperature of 200 degrees Centigrade or less(under full power conditions) has proven to meet the 34 year mean timeto failure specification. Thus, it is highly beneficial to have anefficient device and package system to remove heat.

In general, heat is removed through the source region of each transistorcell in the active area. A source region of the transistor cellcomprises n-doped region 437. In an embodiment of the transistor cell,the via (or opening) for the transistor cell source region is etchedthrough n-doped region 437 into p-doped region 455. First electrodecontact region 495 (58 of FIGS. 1 and 2) is a deposited metal regionover the active area of the RF power IC. The metal of first electrodecontact region 495 fills the via of the transistor cell source regionand couples to both n-doped region 437 and p-doped region 455. The metalin the via of the transistor cell not only makes excellent electricalcontact to the source region but also is a low resistance thermal pathfor removing heat from the die. The metal that contacts region 437 and455 in the bulk silicon is in close proximity to where the heat isgenerated in the transistor cell and thus can remove the heat veryefficiently away from the bulk silicon to first electrode contact region495. Each transistor cell in the active area removes heat in a similarfashion. First electrode contact region 495 is coupled to a sourcepackage lead and heat sink to dissipate heat which will be described inmore detail herein below. As mentioned previously, heat can be pulledfrom both sides of the die. Second electrode contact region 510 iscoupled to a drain package lead that can be coupled to a heat sink tofurther improve the system efficiency to remove heat.

The on-resistance or r_(dson) of the transistor relates to theefficiency of the transistor and the heat generated by the device.Lowering the on-resistance of the RF power transistor reduces thethermal requirements of the package and heat sink. The transistor cellstructure reduces the on-resistance of the transistor. As shown, theconductive path of a transistor comprises first electrode contact region495, n-type region 437, the transistor cell channel, n-type layer 275,n-type epitaxial layer 210, n-type buried layer 205, and secondelectrode contact region 510. First electrode contact region 495 is ametal such as gold which has a low resistance. First electrode contactregion 495 couples to n-type region 437. N-type region 437 is in closeproximity and a low resistance path to the source side of the transistorcell channel. In an embodiment of the transistor cell, the channellength is 0.2-0.3 microns in length. On the drain side of the transistorcell channel n-type layer 275 provides a low resistance path toepitaxial layer 210. The current path of the transistor cell changesfrom a horizontal direction to a vertical direction in n-type layer 275.The main component of r_(dson) for the transistor cell is epitaxiallayer 210. Epitaxial layer 210 has to standoff the voltage applied tothe device. As mentioned previously, the sidewall of dielectric platform255 adjacent to the active area promotes planar breakdown (edgetermination) by preventing curvature of the electric field in epitaxiallayer 210. Planar breakdown allows the use of the lowest resistivityepitaxy to standoff the required voltage thereby minimizing r_(dson) ofthe transistor cell. Epitaxial layer 210 couples to buried layer 205.Buried layer 205 is a highly doped low resistance layer. In anembodiment of the device, a cavity etch is performed in the active areaof the die that further reduces the resistance through buried layer 205(reduces thickness). The conductive path hereinabove applies to eachtransistor cell in the active area, thus the device has been optimizedto have lowest on-resistance possible.

The frequency performance of the RF power transistor is increasedsubstantially by minimizing parasitic capacitances of the device. Inparticular, each transistor cell is optimized to reduce the gate todrain capacitance. The gate to drain capacitance is the dominantcapacitance in relation to the operating frequency because it's valuegets multiplied by the gain of the device. This is known as the Millereffect or Miller multiplied capacitance. In other words, reducing gateto drain capacitance directly improves the bandwidth of the device. Thegate to drain capacitance is minimized by the grounded shielding plateformed adjacent to the gate (polysilicon layers 370 and 410) of thetransistor cell. Grounded shielding plate (labeled 299 in FIG. 21)comprises conductive layers 295, 300, and 305 which forms a lowresistance electrically conductive stack. In an embodiment of thedevice, the grounded shielding plate 299 approximately overlies all ofthe active area except the doped regions (corresponding to p-type dopedregion 380) that define the channel and source regions of eachtransistor cell. Grounded shielding plate 299 is isolated from the topsurface of the die by non-conductive layers 280 and 285 in the activearea of the die except at the periphery of the active area adjacent todielectric platform 255 where conductive layer 295 couples to p-typeregion 310 to make the connection to ground. In general, the source ofthe RF power transistor is coupled to ground when used in a RF poweramplifier. The grounded shielding plate is coupled to ground through thesource regions of transistor cells adjacent to p-type region 310. Asillustrated in FIG. 21, layer 295 of the grounded shielding platecouples to p-type region 310. P-type region 310 is coupled to p-typeregion 380 which in turn couples to p-type region 455. P-type region 455couples to first electrode contact region 495 which couples to thesource region of each transistor cell and ground through a sourcepackage lead. Thus, the electrical path for connecting groundedshielding plate to ground is through bulk silicon of the die which ishighly beneficial because it reduces die area and simplifies theinterconnection scheme of the device.

The grounded shielding plate is placed between the polysilicon gatestructure/gate interconnect and the drain (layer 275 and epitaxial layer210) of the transistor cells. The placement of the grounded shieldingplate converts (or decouples) parasitic gate to drain capacitance intotwo separate capacitors which can be described as a gate to ground(source) capacitance and a drain to ground (source) capacitance. Neitherof these capacitance values are Miller multiplied by the gain of thetransistor cell thereby enhancing frequency performance of the device.Each transistor cell has a centralized source region and a channelregion defined by the gate structure that is circumferential around thesource region. The grounded shielding plate is spaced as close aspossible to the gate. In the embodiment of the device, the groundedshielding plate is isolated from the gate by protective layer 365 on thedrain side of the transistor cell. The protective layer 365 is 500 Åthick, thus the grounded shielding plate is spaced 500 Å from the gate.Similarly, the grounded shielding plate is placed close to the topsurface of the die. In the embodiment, layer 295 of the groundedshielding plate is isolated from the top surface by layers 280 and 285.Layer 280 is an oxide layer having a thickness of approximately 700 Å.Layer 285 is a protective layer having a thickness of approximately 500Å. Thus, grounded shielding plate is approximately 1200 Å from the topsurface of the die.

It should be evident that the grounded shielding plate 299 is placedclose to the edge of the channel on the drain side of the transistorcell. A capacitance value is a direct function of the distance betweentwo conducting surfaces and the dielectric constant of the isolatingmaterial. Fringing capacitance from gate to drain of the transistor celloccurs between the vertical polysilicon gate region (layers 370 and 410)and layer 275. The highest value of fringing gate to drain capacitanceoccurs at the channel boundary to the drain of the transistor cellbecause the spacing between the gate and the drain is the smallest.Thus, the placement of grounded shielding plate as shown has asignificant impact on reducing gate to drain capacitance. Placing thegrounded shielding plate near the edge of the channel of the drain sidemust be balanced against device reliability and creating a large drainto ground capacitance value. Layers 280 and 285 are designed to reliablyisolate the grounded shielding plate from layer 275. Grounded shieldingplate and layer 275 form the conductive plates of a capacitor (drain toground) that covers a substantial portion of the active area. Thethickness and dielectric constant of layers 280 and 285 are a factor inthe total drain to ground capacitance created by the grounded shieldingplate and layer 275. Adjusting the thickness of layers 280 and 285 canbe balanced to determine an optimum value of gate to drain fringingcapacitance versus gate to ground capacitance for maximum deviceperformance. Furthermore, placing grounded shielding plate near the topsurface provides an additional benefit of increasing the breakdownvoltage of the transistor. The grounded shielding plate acts to depletethe top surface of n-type layer 275. This reduces the curvature of thefield lines around p-type region 380 of the transistor cell on the drainside of the channel improving high voltage operation. The improvementcan be substantial. Simulation results of a transistor cell without thegrounded shielding plate for yielded a 60V breakdown which improved to75V with the grounded shielding plate yielding a 25% improvement inbreakdown voltage.

Gate interconnect between transistor cells comprises conductive layers330, 335, and 340. The conductive stack of layers ensures a lowresistance interconnect to the gates of all transistor cells. The gateinterconnect is patterned similarly and approximately overlies thegrounded shielding plate in the active area region. The gateinterconnect and the grounded shielding plate form the conductive platesof a capacitor. They are separated by isolation layers 320 and 325. Thethickness of layers 320 and 325 can be adjusted to decrease the gate toground capacitance value but must be balanced against other transistorcell design tradeoffs such as the depth of the via to ensure good metalcoverage and short thermal path to pull heat from the device. It shouldbe noted that the grounded shielding plate extends over a portion ofdielectric platform 255 to ensure that parasitic gate to draincapacitance is decoupled as the gate interconnect of the active areacouples to control electrode interconnection region 490. Controlelectrode interconnection region 490 is formed overlying dielectricplatform 255 to further minimize gate to drain capacitance. Controlelectrode interconnection region 490 and buried layer 205 formconductive plates of a gate to drain capacitor. Dielectric platform 255has an extremely low dielectric constant and provides separation betweenthe conductive plates greater than the thickness of epitaxial layer 210.Dielectric platform 255 reduces gate to drain capacitance due to controlelectrode interconnection region 490 to an inconsequential value. Thus,parasitic capacitances on a transistor cell level as well as at the dielevel have all been minimized which results in a low r_(dson) radiofrequency power transistor having substantial power gain above 10 GHz.

Typically a RF power transistor is used in a power amplifier operatedwith the source coupled to ground. The drain of the RF power transistortypically swings between ground and the supply voltage of the poweramplifier. In the disclosed embodiment of the device, the RF powertransistor is a n-channel enhancement mode device. An n-channel isformed when a voltage greater than the threshold voltage is applied tothe gate of a transistor cell. The n-channel electrically couples then-type drain to the n-type source to conduct a current. The currentconducted is a function of the applied gate voltage. One characteristicthat affects the performance of the RF power transistor is the dopingprofile of the device. In particular, the doping profile underlying thegate oxide is important as it determines the characteristics of thechannel under different operating conditions. The doping profileunderlying the gate oxide impacts the output impedance of device whichaffects the ability of the RF power transistor to transmit informationin a format such as wideband CDMA.

FIG. 22 is doping profile of a prior art RF power transistor. The dopingprofile corresponds to a RF LDMOS (laterally diffused MOS) transistorwell known to one skilled in the art. The y-axis is the dopingconcentration at the surface of the device. The x-axis is the relativesurface position of the dopings. A gate polysilicon length A correspondsto the drawn or lithographic dimensions of the prior art LDMOS deviceprior to wafer processing. The zero reference point corresponds to thelithographically defined edge of the gate polysilicon on a source sideof the LDMOS transistor. As is well understood, doped regions outdiffuse as thermal cycles of the wafer process occur changing theoriginal dimensions of the RF power transistor. The photolithographicdefined gate polysilicon length A of the example RF LDMOS transistor is1 μm.

A doping profile C corresponds to the doping concentration in thechannel region (underlying the gate oxide) of the RF LDMOS transistor.Doping profile C is a p-type dopant. Doping profile C is formed of anintermediate doping concentration between the source and drain dopingconcentrations. Doping profile C in the channel region is not constantbut varies in concentration from drain to source.

A doping profile B corresponds to the doping concentration of the sourceof the RF LDMOS transistor. Doping profile B is a n-type dopant. Dopingprofile C extends into the source as shown by the dashed line and variesin concentration in the source. Doping profile B has a substantiallyhigher doping concentration than doping profile C. A p-n junction regionD is formed between the n-type doping profile B and p-type dopingprofile C.

A doping profile F corresponds to the doping concentration of the drainof the RF LDMOS transistor. Doping profile F is an n-type dopant. Dopingprofile F is formed adjacent to doping profile C. A p-n junction regionE is formed between n-type doping profile F and p-type doping profile C.In general, doping profile F has a lower doping concentration thandoping profile C. The doping concentration differential between dopingprofile F and doping profile C does not exceed an order of magnitudedifference until more than half way in the channel region towards thesource end of the channel region.

An effective gate length of the RF LDMOS transistor corresponds to thedoping profile C between source region B and drain region F. Theeffective gate length is approximately 0.6 μm which is shorter thanphotolithographic defined gate polysilicon length A. Note that thedoping profile changes in concentration from drain to source. The waferprocess steps used to form the drain, channel region, and source of a RFLDMOS device creates the characteristic doping concentration throughoutthe channel region. Doping profile C has the affect of reducing theoutput impedance of the RF LDMOS transistor due to drain induced barrierlowering. The effective gate length of the RF LDMOS transistor isreduced with increasing drain voltage due to p-n junction E encroachinginto the channel thereby reduce the length of the channel. A factor inchannel length reduction is the area utilized for the space chargeregion in the p-type channel region under high voltage conditions due tolow doping concentrations near the drain. As shown, the dopingconcentration in the channel region does not reach one order ofmagnitude greater than the drain doping concentration untilapproximately at half the distance to the source. Thus, the space chargeregion may encroach a significant distance into the channel regionproducing a wide variation of gate length over the operating range ofthe device. This results in a low output impedance that impacts theperformance of the RF power transistor.

Another fact that is not apparent from the doping profile is asubstantial gate to drain capacitance. The gate to drain capacitanceoccurs because of out diffusion of the drain region under the gate. Thegate to drain capacitance is significant because the value is multipliedby the gain of the device thus it is typically the limiting factor forfrequency response.

FIG. 23 is a doping profile of the RF power semiconductor device of FIG.21 in accordance with the present invention. The y-axis is the dopingconcentration at the surface from the source (region 437) to drain(layer 275) of the device including the channel region (region 380)there between. The x-axis is the position of a doping profile with azero reference point corresponding to a photolithographic (drawn)defined gate polysilicon length G starting at the source side (0 x-axis)of the channel and ending at the drain side (0.28 x-axis). Thephotolithographic defined gate polysilicon length G is approximately0.28 μm for this embodiment of the invention. Both FIGS. 21 and 23 willbe used in the description herein below.

P-type doped region 380 is formed having a doping concentration ofapproximately 1E17 atoms/cm³ as shown in doping profile I. N-type dopedregion 437 is the source of the transistor cell and has a dopingconcentration that has a peak of 1E21 atoms/cm³ at a distance greaterthan −0.1 microns from the zero reference point. A doping profile Hcorresponds to the source of the transistor cell. A portion of p-typedoped region 380 extends into the source of the transistor cell as shownby the dotted line portion of doping profile I. In an embodiment of theRF power transistor, the dotted line portion of doping profile I issubstantially constant within the source of the RF power transistor Ap-n junction J is formed by p-type doped region 380 and n-type dopedregion 437. P-n junction J occurs at approximately 0.05 microns from thezero reference point.

N-type doped layer 275 is formed adjacent to p-type doped region 380.N-type doped region 275 is the drain of the transistor cell and has adoping profile L. In an embodiment of the RF power transistor, thedoping concentration of the drain is approximately 5E14 atoms/cm³. A p-njunction K is formed by p-type doped region 380 and n-type doped layer275 at a distance of 0.28 μm from the zero reference point.

An effective gate length of the RF power transistor is the channellength after all wafer processing steps have been performed. In anembodiment of the RF power transistor, the effective gate length of atransistor cell is approximately 0.2 μm. It should be noted that thedevice structure and the wafer processing steps used to form atransistor cell as described in FIGS. 3-21 yields an approximatelyconstant doping through the channel region of the device in p-type dopedregion 380 between the source and drain. The approximately constantdoping in the channel regions is due in part to the formation of p-typedoped region 380 using three implant energies and doping in quadratureand also that the device does not undergo thermal cycles that would outdiffuse adjacent doped regions to modify the doping concentration inregion 380. Not only is the doping concentration approximately constantin the channel region but the concentration level falls off very rapidlyat p-n junction K. This approximately constant doping is indicated bydoping profile I shown as a solid line from approximately 0.08 to 0.2 onthe x-axis. Doping profile I in the channel of the RF power transistoris near ideal and reduces drain induced barrier lowering.

As mentioned previously, drain induced barrier lowering is a shortchannel effect that changes the channel length as a function of thedrain voltage. The channel length is reduced as the space charge regionof p-n junction K encroaches into the channel region of p-type dopedregion 380 corresponding to an increase in drain voltage. The area takenup by the space charge region in the channel region reduces the channellength at higher drain voltages resulting in a lowering of the outputimpedance. The characteristic constant doping level of doping profile Iwithin the channel region has a rapid falloff in doping concentrationnear p-n junction K. The doping concentration in the channel region(doping profile I) is more than 2 orders of magnitude greater than thedoping level of the drain (doping profile L). Moreover, the dopingconcentration is an order of magnitude greater than the dopingconcentration of the drain at approximately 0.03 μm from p-n junction K.Thus, the space charge region does not encroach significantly into thechannel region because of the high doping concentration. In other words,the effective gate length of the RF power transistor does not varysignificantly as the drain voltage of the device is increased resultingin the RF power transistor having a high output impedance.

It is expected that the RF power transistor will have substantial powergain in 10-20 GHz range, in part due to the effective gate length ofapproximately 0.2 μm. A substantial benefit of the device structure isthat it can be made with wafer processes having critical dimensionsgreater than the effective gate length. In an embodiment of the RF powertransistor, a 0.35 μm wafer process is used to form the device. Ingeneral, the photolithographic critical dimension of a wafer process isnot the limiting factor on the gate length that can be achieved in theRF power transistor. It is the control over the deposition of materialsthat, in part, determines the gate length. In particular, the depositionof polysilicon is the step that affect the gate length.

Another factor in the extended frequency response of the RF powertransistor is reduced parasitic capacitance. In general, the sequence ofwafer process steps described hereinabove is done in a manner thatminimizes out diffusion under the gate. In particular, the sequence ofwafer process steps used to form the device reduces the number ofthermal cycles that cause implants to out diffuse under the gate therebylowering gate to drain capacitance (also known as the Millercapacitance). Device variation from wafer lot to wafer lot is alsominimized.

FIG. 24 is a top view of mesh transistor cells 800 in accordance withthe present invention. Mesh transistor cells 800 are designed to bearrayed or tiled to form a larger RF power transistor comprising aplurality of mesh transistor cells in parallel. The number of meshtransistor cells used to form the device can range from one to hundredsof thousands of transistor cells depending on the required device poweroutput. It should be noted that thermal considerations are a determiningfactor of device power output. A reliable RF power transistor cannot bemanufactured if the heat cannot be removed from the die. Mesh transistorcells 800 corresponds to the transistor cell described in FIGS. 3-21 instructure but differs in the fact that it is designed be arrayed to formthe bulk of the transistors cells in the active area. In the embodiment,mesh transistor cells 800 includes partial mesh transistor cellsadjacent to a central mesh transistor cell. A different transistor cellwould be used near the active area periphery where a mesh transistorcell abuts p-type region 310 (FIG. 21) and completes the area such thatthere are no partial mesh transistor cells left in the transistor cellarray. Mesh transistor cells 800 are formed and replicated in n-typelayer 275 (FIG. 21). This allows each mesh transistor cell of meshtransistor cells 800 to conduct current from all sides (360 degrees)around each source region. Conversely, the transistor cell shown inFIGS. 3-21 is a transistor cell that abuts p-type region 310 (FIG. 21)on one side of the transistor cell near the dielectric platform. Thetransistor cell of FIGS. 3-21 cannot conduct on the side where thechannel abuts p-type region 310 but will conduct in all other directionsinto n-type layer 275. P-type region 310 prevents the channel fromcoupling to n-type layer 275 thereby preventing a conductive path fromdrain to source when a gate voltage inverts the channel region to forman n-channel.

The transistor cell configuration disclosed herein has substantialadvantages due to the efficiency in device structure in reducingparasitic resistances, capacitances, and inductances as well as improvedlinearity, distortion, power density, and frequency response whencompared to prior art RF power transistors using an interdigitatedfinger geometry. An example of an interdigitated finger transistor is RFLDMOS (laterally diffused MOS). LDMOS transistors comprise longalternating stripes of drain and source regions separated by the channelregion. A large transistor is formed by connecting the gate regions incommon and a top surface gate contact region is provided. Similarly, thedrain regions are coupled in common and a drain contact region isprovided. The source contact region is on a back surface of the die. Thesource regions are coupled to the source contact region through lowresistance sinkers that are formed in the substrate. The low resistancesinkers increase the size of the die and source regions. A device ofthis type will typically have a current density of approximately 40-50microamperes per micron of device Z (width).

The mesh transistor structure disclosed herein greatly increases thecurrent density per square micron of transistor area. Part of theefficiency increase is a direct function of the mesh transistor topologywhich allows closely spaced transistor cells that generate a largetransistor Z/L ratio per unit area. A first difference between meshtransistor cell 800 and an LDMOS structure is that the source and draincontact regions are on different sides of the die. In mesh transistorcell 800 the source contact region is on the top side of the die and thedrain is on the back side of the die. A second difference is that meshtransistor cell has a centralized source region having a channel regionthat is formed circumferentially around the source region. As mentionedpreviously, mesh transistor cell 800 conducts current a full 360 degreesaround the source region (except the transistor cells adjacent to thedielectric platform (blocked by p-type region 310). A third differenceis that the drain of each transistor cell is common to one another. Inthe disclosed embodiment, the epitaxial layer 210 (FIG. 21) is the drainof each transistor cell which comprises the RF power transistor. Thus,the transistors of mesh transistor cell 800 are vertical transistors(not lateral devices coupled in common). A fourth difference is the gateinterconnect between mesh transistor cells. This is shown in FIGS. 24and 25 and will be described in more detail herein below. The gateinterconnection results in an extremely low gate resistance.

Mesh transistor cells 800 comprises a single centrally located meshtransistor cell and four partial transistor cells. The four partialcells are located symmetrically around the complete mesh transistorcell. Layers above the gate interconnect are not shown to betterillustrate features of mesh transistor cells 800. For example, layerscorresponding to first electrode interconnection region 495 (FIG. 21)and the underlying isolation layers (layers 425, 460, and 465 of FIG.21) are not shown. The four partial transistors cells are one fourth ofa single mesh transistor cell. Mesh transistor cells 800 are tiled inboth the x and y direction. Tiling mesh transistor cells 800 is aprocess of replicating the cell and abutting cells next to one another.

In an embodiment of the device, the channel region formedcircumferentially around the central mesh transistor of mesh transistorcells 800 has eight sides. The eight sided shape of the channel regioneliminates sharp 90 degree corners that could lead to non-uniformchannel length. Interior to the circumferential channel is a sourceregion of the transistor cell. A preohmic (or via) region 810 is anopening formed to expose the source region of each mesh transistor cell.In general, a metal (not shown) overlies preohmic regions 810 fillingthe opening and coupling to each source to form a first electrodeinterconnection region (coupling the sources of the mesh transistorcells in common). The first electrode interconnection region correspondsto the first electrode interconnection region 495 of FIG. 21 Apolysilicon layer 820 couples to the first electrode region andcorresponds to polysilicon layer 410 within the source region of a meshtransistor cell. Polysilicon layer 820 couples to the source region ofthe mesh transistor and increases the vertical surface area forcontacting the metal that fills preohmic region 810.

A gap 850 corresponds to the separation or spacing between polysiliconregions of mesh transistor cell 800. In particular, gap 850 shows theseparation between polysilicon layers 820 and a polysilicon layer 840. Aprotective layer (not shown) separates polysilicon layer 820 frompolysilicon layer 840. The protective layer corresponds to protectivelayer 460 of FIG. 18 which separates polysilicon in the source from thepolysilicon which forms the gate and gate interconnect. Polysiliconlayer 840 comprises a gate of each mesh transistor cell and the gateinterconnect that couples to gates of adjacent transistor cells.Polysilicon layer 840 corresponds to polysilicon layer 410 (FIG. 21)that couples to polysilicon layer 370 of FIG. 21. The combination ofpolysilicon layers 370 and 410 form the gate of each mesh transistorcell and the horizontal width or thicknesses of the polysilicon layersdetermines the gate length. Polysilicon layer 830 couples to polysiliconlayer 840 which is used to lower the control electrode resistance.Polysilicon layer 830 corresponds to polysilicon layer 330, tungstensilicide layer 335, and polysilicon layer 340 that are coupled in common(as shown in FIG. 21) and are used to couple the gate (polysilicon layer370 of FIG. 21) to control electrode interconnection region 490 on theperiphery of the die. Thus, the gates of each mesh transistor cell canbe coupled together in a fashion that results in an extremely lowresistance path.

FIG. 25 is a top view of an array 801 of mesh transistor cells inaccordance with the present invention. Array 801 illustrates meshtransistor cell 800 of FIG. 24 replicated and tiled together to form aplurality of transistor cells coupled in parallel to form a RF powertransistor in the active area of the die. Note that partial meshtransistors cells are shown on the periphery of the array. Typically,additional mesh transistor cells (not shown) would be tiled to the arrayto form complete transistor cells on the periphery such that onlycomplete transistors comprise the finished array used to form the RFpower transistor. The top view of array 801 is useful to show how themajority of the heat is pulled from the transistor die. Each preohmic(or via) centrally located in each mesh transistor cell when filled withmetal to form first electrode interconnection region 495 (FIG. 21) formsa thermal conduction path comprising the bulk silicon, metal in thepreohmic, first electrode interconnection region (metal that couples allof the mesh transistor cell sources together), package lead, andexternal heat sink. Pulling heat from the top side of the die in closeproximity to where the heat is generated is a very efficient way ofremoving heat.

Semiconductor Package

A semiconductor package for a radio frequency (RF) power transistor die,such as the die described above, must adequately perform severalfunctions. First, it houses the power transistor die and thus isolatesthe die from harmful elements from the external environment that canaffect the performance and reliability of the die. For example, humidityis often a problem that can produce corrosion and ultimately the failureof the device. Second, a power transistor generates substantial amountsof heat. Consequently, the power transistor package of this invention isdesigned to be a thermal conductor that channels the heat away from thedie. The ability to effectively remove heat greatly impacts deviceperformance. A transistor operating at a lower temperature is morereliable and has better performance characteristics than a deviceoperating at a higher temperature. Finally, a power transistor istypically coupled to a printed circuit board or module to form anamplifier circuit. The semiconductor package has electrical leads orcontacts that couples the power transistor die to the printed circuitboard. The package itself can add parasitic resistance, inductance, andcapacitance that can greatly degrade the performance of the powertransistor.

FIG. 26 is a top view of a prior art semiconductor package 509 for a RFpower die 511. Semiconductor package 509 comprises a die mount 512, aceramic mount ring 513, a gate lead 514, and a drain lead 515. In thisexample, RF power die 511 is a MOS power transistor having a drain, agate, and a source.

Die mount 512 acts as an electrical interconnect, a heat sink/thermalpath, and strong supportive area for mounting RF power transistor 511.Die mount 512 is typically made of a metal having good electrical andthermal conductive characteristics such as copper or a copper alloy. Anupper surface of die mount 512 on which die 511 is mounted is planar.Ceramic mount ring 513 defines the area in which die 511 is placed. Inother words, the cavity formed by ceramic mount ring 513 is sufficientlylarge to allow die 511 to be placed with the opening. Ceramic mount ring513 is made of a non-conductive ceramic material. The source contact ofdie 511 is the backside of the die. Typically, a metal layer is formedon the backside of the die to form a low resistance source contact. Thesource contact of die 511 is soldered to die mount 512 within the cavityformed by ceramic mount ring 513.

The top side of die 511 includes gate contacts and drain contacts. Ingeneral, die mount 512 is rectangular in shape, gate lead 514 and drainlead 515 oppose one another and extend beyond an edge of die mount 512to simplify connection to package leads. Gate lead 514 and drain lead515 are made of metal and comprise a substantial area to reduceresistance and inductance. Gate lead 514 is fastened to ceramic mountring 513 to electrically and physically isolate it from die mount 512.Similarly, drain lead 515 is mounted on the opposing side of ceramicmount ring 513.

As mentioned previously, ceramic mount ring 513 is non-conductive sogate lead 514 and drain lead 515 are not electrically coupled togethernor to die mount 512. Gate lead 514 is electrically coupled to the gateof die 511 through a number of gate wire bonds 516. Similarly, drainlead 515 is electrically coupled to the drain of die 511 through anumber of drain wire bonds 517.

It should be noted that RF power transistor die 511 has a long andnarrow aspect ratio. This is done intentionally to minimize the lengthof gate wire bonds 516 and drain wire bonds 517 to reduce inductance. Ingeneral, a radio frequency power transistor operating at highfrequencies and power will have a large active transistor area thatrequires more than one drain wire bond. In fact, distribution of thewire bonds is critical to minimize the resistive path to active areas ofthe RF power transistor die 511.

A cap (not shown) is placed on and fastened to an upper surface ofceramic mount ring 513 such that the cavity is covered therebyprotecting the gate wire bonds 516, drain wire bonds 517, and die 511from the external environment.

Semiconductor package 509 is a low cost package that has been widelyused for RF power transistors operating at frequencies up to 2gigahertz. One aspect of semiconductor package 509 is die mount 512which contacts the source of die 511 through the backside of the die.Typically, the source of die 511 is coupled to ground in an amplifierapplication. Electrically coupling through the backside of RF powertransistor 511 provides a large thermal pathway to die mount 512 todissipate heat.

Unfortunately, the use of gate wire bonds 516 and drain wire bonds 517causes unwanted problems. Gate wire bonds 516 and drain wire bonds 517add parasitic resistance and inductance to RF power transistor 511. Thishas proven problematic at best and can severely degrade the performanceof the device, for example transistor bandwidth. In particular, gatewire bonds 516 and drain wire bonds 517 are in series respectively withgate lead 514 and drain lead 515. Die 511 operating at high frequencieshas reduced operating efficiency due to the parasitic inductance. Shuntcapacitors are often added to reduce the problems due to parasiticinductance. A shunt capacitor could be added in parallel with gate wirebonds 516 or drain wire bonds 517. However, the shunt capacitors have tobe matched to the actual parasitic inductance such that the inputimpedance of semiconductor package 509 matches the impedance of theexternal circuit driving the device. Impedance mismatch due to variationin capacitance or inductance values results in a loss of efficiency.Adding shunt capacitors to semiconductor package 509 to reduce thesehigh frequency problems also increases cost.

Perhaps more important is the fact that parasitic electrical componentsand thermal transfer characteristics of semiconductor package 509degrades the bandwidth and the linearity of the device. Linearity is animportant characteristic. In general, parasitics change the operatingcharacteristics of a radio frequency device to be more non-linear.Linearity is critical in the ability of a device to transmit informationaccurately. For high speed wireless data applications, the amount ofchannels that can be operated in a given bandwidth is directly relatedto the linearity of the power amplifier. Using power transistors thathave non-linear characteristics generates noise signals that are coupledto adjacent channels. Data can be lost if the noise is high enough.Moreover, the main solution to reduce this problem is to increase thebandwidth of each channel thereby decreasing the amount of channels thatcan be transmitted over a given bandwidth.

FIGS. 27-28 are substantially similar to FIGS. 1-2 previously discussedbut are included in this point of the discussion of the package aspectsof this invention for ease in reference. FIG. 27 is a top view of aradio frequency (RF) power transistor die 520 in accordance with thepresent invention. RF power transistor die 520 has a first electrodeinterconnection region 521 and control electrode interconnection region522 on a first major surface of RF power transistor die 520. A secondelectrode interconnection 510 region (see, e.g., FIG. 21)) is providedon a second (bottom) major surface of 520.

As mentioned previously, a radio frequency power semiconductor deviceaccording to this invention finds particular (but not exclusive) utilityas a device that operates at frequencies greater than 500 megahertz anddissipates more than 5 watts of power for purposes of describing theradio frequency package disclosed herein. In particular, a RF powertransistor in cellular communication gear is operated under some of themost severe conditions when compared to other devices. For example, in aclass-A power amplifier the transistor is biased to a level where thedevice is dissipating about the maximum power output of the amplifiercontinuously, 24 hours a day, 365 days a year. Class-A operation isdesirable in a cellular RF power amplifier for increased linearity. Thetransistor and package are designed to meet these thermalcharacteristics with an expected mean time to failure exceeding 34years. In general, the die must be maintained at a temperature 200degrees centigrade or less to achieve the mean time to failurespecification. Lowering the temperature greatly increases devicereliability. Thus, the package interaction to the die is critical inboth the electrical and thermal performance. Moreover, RF high powertransistor device specifications are probably the most difficult to meetand thus the transistor/package disclosed herein is capable of meetingthe needs of almost all other discrete transistor applications.

In an embodiment of RF power transistor die 520, first electrodeinterconnection region 521, control electrode interconnection region522, and the second electrode interconnection region are respectivelycoupled to a source, gate, and drain of RF power transistor die 520.Other embodiments are also possible using this contact scheme fordifferent device types. First electrode interconnection region 521 is anexposed metal layer centrally located over the active area of RF powertransistor die 520. Ideally, first electrode interconnection region 521has multiple connections distributed throughout the active area of RFpower transistor die 520 to the source of the die 520 to minimize thecontact resistance to each transistor cell. The use of first electrodeinterconnection region 521 to connect to the source of an MOS device isfor illustrative purposes only and can be used for device regionsdepending on the semiconductor device configuration.

In an embodiment of RF power transistor die 520, control electrodeinterconnection region 522 is formed as a ring around first electrodeinterconnection region 521. The ring is an exposed metal layer thatcouples to the gate of RF power transistor die 520. In general, the samemetal interconnect layer of the wafer process would be used to form bothfirst electrode interconnection region 521 and control electrodeinterconnection region 522 thereby making them substantially planar toone another. A space 523 comprises an insulative material such assilicon dioxide for electrically isolating first electrodeinterconnection region 521 from control electrode interconnection region522. Forming the control electrode interconnection region 522 as a ringallows interconnection from all sides of the active area to minimize theresistance of the connection. Ideally, control electrode interconnectionregion 522 is formed to reduce parasitic capacitance coupled to the RFpower transistor to increase performance and linearity.

In an embodiment of RF power transistor die 520, solder is used tocouple first electrode interconnection region 521 and control electrodeinterconnection region 522 to leads of a package. Space 523 issufficiently wide to prevent any potential bridging of the solder eitherduring its initial application or in other subsequent reflow steps.Although control electrode interconnection region 522 is shown as acontinuous ring around first interconnection region 521 it could be madein separate pieces if beneficial. Similarly, first electrodeinterconnection region 521 is not required to be a contiguous metallayer but could be broken into more than one contact. In one embodiment,forming control electrode interconnection region 522 as a contiguousring is desirable for making a hermetically sealed package as will bedescribed in more detail hereinafter. Control electrode interconnectionregion 522 as a gate contact is for illustrative purposes only and canbe used as a gate or drain contact depending on the semiconductor deviceconfiguration.

In an embodiment of RF power transistor die 520, the RF power transistoris formed in an epitaxial layer 525. Epitaxial layer 525 underlies firstelectrode interconnection region 521. In an embodiment of RF powertransistor die 520, a dielectric platform 524 is an isolation regionthat comprises a dielectric material. Control electrode interconnectionregion 522 overlies dielectric platform 524 to reduce parasiticcapacitance. Dielectric platform 524 reduces gate to drain capacitanceand increases a breakdown voltage of the RF power transistor.

As described above a metal layer 510 (FIG. 21) is formed on the backsideof the substrate as the second electrode interconnection region. Themetal layer is a low resistance electrical conductor coupling to thesubstrate. Solder can be applied to the metal layer for coupling to alead. The second electrode interconnection region corresponding to thedrain of the device is for illustrative purposes only and can be otherelectrodes of a RF power device depending on the configuration.

FIG. 28 is a cross-sectional view of radio frequency power transistordie 520 of FIG. 27. RF power transistor die 520 has a first majorsurface and a second major surface. On the first major surface of RFpower transistor die 520, first electrode interconnection region 521 andcontrol electrode interconnection region 522 are exposed for coupling toleads of a RF package. In an embodiment of die 520, first electrodeinterconnection region 521 is centrally located on the first majorsurface. Furthermore, the active area of die 520 substantially underliesfirst electrode interconnection region 521 to ensure maximum thermaltransfer and minimum resistance when coupled to leads of the RF packagedisclosed herein. The active area of die 520 is the area wheretransistor cells of RF power transistor die 520 are formed.

Control electrode interconnection region 522 is formed in a ring aroundfirst electrode interconnection region 521. In an embodiment of die 520,a dielectric platform 524 underlies control electrode interconnectionregion 522. Dielectric platform 524 is an isolation region comprisingdielectric material that separates control electrode interconnectionregion 522 from an epitaxial layer 525 and a buried layer 538 of die520. Dielectric platform 524 reduces a gate to drain capacitance andincreases a breakdown voltage of the RF power transistor.

In an embodiment of the RF power transistor, die 520 comprises asubstrate 536, a buried layer 538 overlying substrate 536, and epitaxiallayer 525 overlying buried layer 538. In an embodiment of die 520, thesecond major surface is masked, patterned, and etched. The etch removessubstrate 536 in the non-masked areas forming a cavity 537. Buried layer538 is used as an etch stop because it is doped an opposite type assubstrate 536. A portion of substrate 536 remains near the periphery ofdie 520. The remaining portion of substrate 536 forms a ring or framethat stiffens and supports the thin active area of the RF powertransistor overlying cavity 537. Thinning die 520 aids in lowering Rdsonof the device and the thermal resistance to remove heat. The secondelectrode interconnection region 501 is formed in cavity 537 overlyingexposed buried layer 538. The shape of cavity 537 is useful in aligninga lead to contact the second electrode interconnection region as will bedescribed later herein below.

FIG. 29 is a top view of a RF power transistor package 540 in accordancewith an embodiment of the present invention. RF power transistor package540 comprises a first external contact or lead 541, a second lead 542, athird lead 543, and an isolation ring 544. First lead 541, second lead542, and third lead 543, respectively correspond to a source lead, gatelead, and drain lead. RF power transistor die 520 of FIGS. 27 and 28 ismounted in package 540.

A die mount pedestal 545 underlying RF power transistor die 520 iscentrally located on first lead 541. Die mount pedestal 545 is formed onfirst lead 541 as a raised area that has a surface area smaller than die520. This configuration allows both the first and control electrodeinterconnection regions of die 520 to be coupled respectively to lead541 and lead 542 in a manner that is easily manufactured, reducesparasitic resistance/capacitance/inductance, and removes heat from thedie efficiently.

An insulation ring 544 surrounds die 520 and die mount pedestal 545Insulation ring 544 is made of a non-conductive material such as aceramic or plastic material. In an embodiment of RF power transistorpackage 540, insulation ring 544 is made of a ceramic material.

First lead 541 is a contact that provides external connection to thefirst electrode interconnection region 521 on die 520. In such manner,access is obtained to the sources of the transistor cells. First lead541 is a metal lead, typically copper, copper-tungsten alloy, or otherlow resistance thermally conductive metal. Referring to back to FIG. 27,die mount pedestal 545 couples to first electrode interconnection region521 of FIG. 27. Die mount pedestal 545 is made of electricallyconductive material and is coupled to first lead 541. Pedestal 545 couldbe formed integral with lead 541, if desired. As mentioned previously,the source of a RF power transistor is typically coupled to ground.

Referring back to FIG. 29 first lead 541 has extremely low resistanceand inductance. In an embodiment of package 540, inductance is minimizedby coupling first lead 541 to first electrode interconnection region521. In particular, the large surface of die mount pedestal 545 iscoupled to first electrode interconnection region 521 through anelectrical and thermal conductive material such as solder or conductiveepoxy. The electrical and thermal conductive material physicallyattaches first electrode interconnection region 521 to die mountpedestal 545. It should be noted that first electrode interconnectionregion 521 substantially overlies the active area of the RF powertransistor. Thus, coupling first lead 541 essentially directly theretoresults in low resistance, low thermal resistance, and low inductance ascompared to the use of conventional wire bonds.

Referring also to FIG. 32, the large exterior surface of first lead 541when coupled to a printed circuit or power amplifier module groundprovides an ideal electrical and thermal coupling. Removing heat is animportant factor in RF device performance and long-term reliability.First lead 541 will often be coupled to a heat sink on a printed circuitboard 546 to efficiently remove heat. Liquid cooled or forced air heatsinking is useful to bring die temperatures lower when operating at highpower such as when the printed circuit board 546 is part of atransmitter in a cellular base transceiver station.

Second lead 542 is mounted to isolation ring 544. Inner portions ofsecond lead 542 are electrically connected to a metal layer formedwithin or on isolation ring 544. Inner portions of the metal layercorrespond in shape to the annular control electrode interconnectionregion 522 of FIG. 27 in the form of an interconnect ring. This will beshown in greater detail herein below. The inner interconnect ring ofisolation ring 544 is further electrically coupled by way of the metallayer to an outer interconnect region on isolation ring 544 where secondlead 542 is attached. Thus, the control (gate) electrodes of the cellscomprising the RF power transistor are also coupled to second externalmetal lead 542 without wire bonds. The interconnect between second lead542 and control electrode interconnection region 522 is low inresistance and low in inductance. Inductance and resistance are greatlyreduced when compared to prior art packages. Furthermore, the gate tosource parasitic capacitance due to first lead 541 and second lead 542can be kept to a minimum by utilizing a low k dielectric material forisolation ring 544 and spacing each away from one another. Also, it isbelieved that no shunt capacitors are required yet the maximum useablefrequency response of die 520 is achieved through the design of RF powertransistor package 540.

Third lead 543 is coupled to the drain interconnection 510 of die 520.Referring back to FIG. 27, third lead 543 directly connects to thebackside drain interconnection 510 (FIG. 21). Third lead 543 is coupledto the second major (back side) surface of die 520. Wire bonds are againnot used in providing external connection to the drain of the powertransistor. Die 520 has significantly reduced parasitic resistance andinductance when packaged in accordance with the teachings of thisinvention, resulting in little or no loss in operating efficiency.Furthermore, third lead 543 provides another heat sink for die 520.Since third lead 543 contacts a large portion of the die 520, it is anexcellent thermal pathway to remove heat. RF power transistor package540 is almost a perfect thermal conductor to remove heat from die 520because it has the capability to remove heat from both the top andbottom of the die 520.

Having two thermal paths allows more choices in a thermal strategy inthe operation of the RF power transistor die 520. In a first strategy,additional external heat sinks can be coupled to both first lead 541 andthird lead 543 to rapidly remove heat from RF power transistor die 520and operate at as low a die temperature as possible. A second strategyregulates the temperature of the die to minimize temperaturefluctuations. A stable or constant die temperature greatly reducesthermally induced non-linearities in the RF power transistor due tochanging operating conditions. Non-linear behavior by the RF powertransistor generates distortion components that affect power amplifierperformance in radio frequency applications.

FIG. 30 is an illustration of a first lead 541 of a radio frequencypower transistor package 540. First lead 541 electrically couples tofirst electrode interconnection region 521 of FIG. 27 and is a thermalpath for conducting heat away from the die 520 of FIG. 2. First lead 541typically is made from metal, for example copper or copper-tungstenalloy. First lead 541 comprises a main body 541 and die mount pedestal545. First lead 541 can be mounted such that a major surface 550 iscoupled to a substrate or a heat sink. First lead 541 is sized to be asubstantial thermal mass and low resistance contact. Die mount pedestal545 is shaped similarly to first electrode interconnection region 521 ofFIG. 27. The surface of die mount pedestal 545 is equal to or smallerthan first electrode interconnection region 521. In general, lead 541and die mount pedestal 545 are made of the same material and can beformed from a single piece of metal using a stamping process, a castingprocess or other manufacturing process known to one skilled in the art.

FIG. 31 is a top view of first lead 541. In an embodiment of package540, die mount pedestal 545 is centrally located on first lead 541.Typically, lead 541 is substantially larger than radio frequency powertransistor die 520 of FIG. 2. Lead 541 forms a large thermal mass forpulling heat from die 520. The large size also reduces the resistance oflead 541. Slots can be formed in first lead 541 to simplify fastening ofthe package to a heat sink or substrate.

FIG. 32 is a cross-sectional view of RF power transistor package 540.Isolation ring 544 overlies a major surface of first lead 541. The firstelectrode interconnection region 521 of RF power transistor die 520couples to die mount pedestal 545 of first lead 541. A portion of die520 overlies isolation ring 544.

The interconnect ring formed on isolation ring 544 couples to controlelectrode interconnection region 522 of die 520. The interconnect ringon isolation ring 544 forms a contact region on isolation ring 544.Second lead 542 couples to the contact region on isolation ring 544 thuscoupling second lead 542 to the control electrode interconnectionregion.

An annular collar or isolation ring 555 overlies isolation ring 544.Isolation ring 555 aids in the alignment of third lead 543 to die 520.Isolation ring 555 also aids in forming a hermetic seal to isolate die520 from an external environment. Isolation ring 555 is made from anon-conductive material such as ceramic or plastic. In an embodiment ofpackage 540, second lead 542 is exterior to isolation ring 555.

Third lead 543 couples to the second electrode interconnection region501 on the second major surface of die 520. Note that third lead 543 isshaped complementarily to the cavity defined by ring 555.

In particular, a contact surface is shaped similar to the second majorsurface of die 520 to couple to the second electrode interconnectionregion. Third lead 543 includes outer walls that slidingly fit withinthe inner walls of isolation ring 555 to aid in aligning the lead 543with die 520 during assembly. Third lead 543 also has a portion thatextends over an upper surface of isolation ring 555. This feature or lipof third lead 543 attaches to the upper surface of isolation ring 555forming a hermetic seal.

FIG. 33 is an enlarged cross-sectional view of the package 540illustrated in FIG. 32. In particular, the central area of package 540where the RF power transistor die 520 is coupled to first lead 541,second lead 542, and third lead 543 is shown in more detail.

In an embodiment of the RF power transistor, the first electrodeinterconnection region 521 is centrally located on the first majorsurface of die 520 overlying the active area of the device while thecontrol electrode interconnection region 522 is formed as a ring aroundthe first electrode interconnection region 521. First lead 541 includesdie mount pedestal 545 that couples to the first electrodeinterconnection region 521 of die 520. Isolation ring 544 couples tofirst lead 541 and includes an opening which die mount pedestal 545protrudes. Die mount pedestal 545 is approximately the same size as thefirst electrode interconnection region 521 or smaller to preventshorting to the third electrode interconnection region. Isolation ring544 is made from a non-electrically conductive material. In anembodiment of package 540, the surfaces of isolation ring 544 and diemount pedestal 545 are parallel to one another but the surface die mountpedestal 545 is above the surface of isolation ring 544.

In general, die mount pedestal 545 electrically couples to the firstelectrode interconnection region 521 of die 520. Die mount pedestal 545couples to the active area of the first major surface of die 520 toprovide a thermal path to remove heat from die 520 through first lead541. In particular, die mount pedestal 545 couples to the majority ofthe active area of the RF power transistor that is conducting asubstantial current. In an embodiment of package 540, first lead 541 ismade of metal such as copper or copper-tungsten alloy and is physicallyand electrically coupled to the first electrode interconnection region521 by a solder layer 558, electrically conductive epoxy or otherequivalent means.

Outer edges of die 520 overhang die mount pedestal 545. In oneembodiment the control electrode interconnection region 522 is formed asa ring around the first electrode interconnection region 521. Thecontrol electrode interconnection region 522 is on the region of die 520that overhangs die mount pedestal 545. The amount of overhang isapproximately the same on each side of die mount pedestal 545.

Isolation ring 544 underlies the region of die 520 that overhangs diemount pedestal 545. As mentioned previously, isolation ring 544 isplaced such that a first major surface overlies first lead 541 and isadjacent to die mount pedestal 545. In this embodiment, second lead 542does not directly contact die 520. Second lead 542 is supported by asecond major surface of isolation ring 544. Isolation ring 544 includesa metallic layer or interconnect 561 that couples lead 542 to thecontrol electrode interconnection region 522 of die 520. Interconnect561 may be formed on or within isolation ring 544.

Isolation ring 544 is a non-electrically conductive, non-porous materialsuch as ceramic, plastic, or organic material. Isolation ring 544 isbonded or attached to first lead 541 in a sealed manner. In anembodiment of package 540, the second major surface of isolation ring544 is below a surface of die mount pedestal 545. The height differencebetween the second major surface of isolation ring 544 and the surfaceof die mount pedestal 545 accommodates solder 557 that couples thecontrol electrode interconnection region 522 on die 520 to interconnect561 on isolation ring 544. For example, interconnect 561 is formed in acorresponding ring shape that aligns to the control electrodeinterconnection region 522. Coupling the ring shaped portion ofinterconnect 561 to the control electrode interconnection region 522with solder 557 seals a perimeter of die 520, hermetically sealing theactive area of die 520 from an external environment. Other materialssuch as a conductive epoxy could be used in place of solder 557.

Isolation ring 555 overlies isolation ring 544. Die mount pedestal 545protrudes through the opening in isolation ring 555. Isolation ring 555separates second lead 542 from third lead 543, aids in the alignment ofthird lead 543 to RF power transistor die 520, and is part of thehousing of RF power transistor package 540. Isolation ring 555 is anon-electrically conductive, non-porous material such as a ceramic,plastic, or organic material.

Isolation ring 555 does not have to be a separate component but can beformed as part of isolation ring 544. If isolation ring 555 is aseparate component, it is attached to isolation ring 544 by anappropriate methodology that physically holds it in place and is sealed.In an embodiment of package 540, isolation ring 555 is coupled orfastened to interconnect 561 on isolation ring 544. As shown, sharpcorners on isolation ring 555 are chamfered to reduce stress on thematerial.

Isolation ring 555 includes a inwardly projecting finger region 559 thatunderlies an edge of die 520 to provide support for outer portions ofdie 520. Third lead 543 is shaped to fit within isolation ring 555. Inan embodiment of the RF power transistor, the second major surface ofdie 520 is etched to have a predetermined shape. Third lead 543 isshaped similarly to the etched second major surface of die 520 to aid incoupling third lead 543 to die 520. An inner wall of isolation ring 555retains third lead 543 from moving a significant distance laterally. Anupper surface of isolation ring 555 also supports and seals to thirdlead 543 as it extends beyond the package. Third lead 543 is attached tothe upper surface of isolation ring 555 to hermetically seal die 520from an external environment.

Third lead 543 physically and electrically couples to the secondelectrode interconnection region 501 on the second major surface of die520. Third lead 543 is coupled to the second electrode interconnectionregion 501 using solder, conductive epoxy or other equivalent means. Asshown, the second electrode interconnection region 501 is located in acavity 537 as shown in FIG. 28 that aids in alignment when couplingthird lead 543 thereto. In an alternate embodiment, the second majorsurface of die 520 is planar. Third lead 543 then couples to the secondelectrode interconnection region 501 on the planar second major surfaceof die 520. Isolation ring 555 aids in aligning third lead 543 to thesecond electrode interconnection region in this alternate embodiment. Ineither case, third lead 543 is coupled to the second electrodeinterconnection region 501 of the RF power transistor.

Third lead 543 is made of metal such as copper or copper-tungsten alloy.Third lead 543 is a thermal path for removing heat from die 520. Thus,RF power transistor package 540 minimizes lead inductance by couplingfirst lead 541 and third lead 543 to die 520 without wire bonds. Thethermal resistance of package 540 is substantially reduced by removingheat from both sides of die 520 through first lead 541 and third lead543. Moreover, package 540 simplifies assembly and lowers manufacturingcosts of a high power radio frequency transistor.

FIG. 34 is a further magnified view of RF power transistor package 540of FIG. 33. The magnified view better illustrates how components of RFpower transistor package 540 are attached together. In an embodiment ofpackage 540, the first major surface of isolation ring 544 has ametallic layer 587 for coupling with first lead 541. Metallic layer 587is bonded securely to the first major surface. In an embodiment whereisolation ring 544 is a ceramic material, a high temperature reflowprocess can be performed to bond metallic layer 587 to first lead 541.The high temperature reflow process securely fastens isolation ring 544to first lead 541 such that subsequent manufacturing steps do not affectbonding.

Second lead 542 and isolation ring 555 are coupled to the second majorsurface of isolation ring 544. In an embodiment of package 540,interconnect 561 is formed on the second major surface of isolation ring544. A bottom surface of isolation ring 555 includes a metallic layer589. Metallic layer 589 is securely fastened to isolation ring 555. Inan embodiment of package 540, isolation ring 555 is made of ceramic. Ahigh temperature reflow process can be performed to bond metallic layer589 to interconnect 561. Other known high temperature couplingmethodologies can also be used. In an embodiment of package 540, secondlead 542 abuts isolation ring 555 and is coupled to interconnect 561 onisolation ring 544 by a high temperature solder. The physical attachmentof second lead 542 and isolation ring 555 to isolation ring 544 is notaffected by subsequent manufacturing steps to produce package 540.

Solder 557 and solder 558 are used to respectively couple controlelectrode interconnection region 522 of die 520 to interconnect 561 onisolation ring 544 and first electrode interconnection region 521 to diemount pedestal 545. Solder 588 couples third lead 543 to the secondelectrode interconnection region 501 on the second major surface of die520. In an embodiment of package 540, the upper surface of isolationring 555 includes a metallic layer 575 formed thereon. Solder 583couples third lead 543 to the upper surface of isolation ring 555 suchthat lead 543 and isolation ring 555 form a hermetic seal to isolate die520 from an external environment.

A methodology for assembling radio frequency power transistor package540 begins with two assemblies. A first assembly is made by physicallyand electrically attaching die 520 to third lead 543. Third lead 543 canthen be used as a handle to move and position die 520 for subsequentsteps. The attachment methodology of third lead 543 to die 520, forexample solder 588, is selected to be unaffected by subsequentmanufacturing or thermal steps to form package 540.

A second assembly comprises first lead 541, isolation ring 544,isolation ring 555, and second lead 542. Isolation ring 544 is attachedto first lead 541. Isolation ring 555 is attached to isolation ring 544.Second lead 542 may also be attached to interconnect on isolation ring544 if desired or can be attached in a later step. Similar to thatdescribed above, the attachment processes employed are unaffected bysubsequent manufacturing or thermal steps to form package 40.

Solders 557, 558, and 583 are placed on a predetermined surface. Thesurface on which the solder is placed is selected to simplify and ensureuniform solder placement. For example, solder 583 can be placed on thirdlead 543, metal layer 575, or both. In an embodiment of package 540,lead 543 and die 520 is fitted within the opening of isolation ring 555.Solder 557 is coupled between control electrode interconnection region522 of die 520 and interconnect 561. Solder 558 is coupled between firstelectrode interconnection region 521 of die 520 and die mount pedestal545. Finally, solder 583 is coupled between third lead 543 and metallayer 575. Package 540 can be placed in an oven, furnace or hot platesso that solders 557, 558, and 583 reflow to form a physical bondingconnection.

The amount and thickness of solder 557, 558, and 583 are selected toensure consistent connections are formed under the tolerances andvariations of the manufacturing process. It may also be beneficial toutilize solders of different temperatures to allow one solder to reflowbefore another. Pressure may also be applied to package 540 to ensurecoupling of solders 558, 558, and 583 during the reflow process.

FIGS. 35-42 illustrate an alternative embodiment for the package of thisinvention. In this embodiment the die 520′ is shown has a flat thinnedwafer instead of the die 520 having the backside cavity formed therein.The external lead for the drain in this embodiment has two parts: adrain stub 600 and a terminal 602. The drain stub 600 has an innerportion which is substantially complementary with the secondinterconnection region 501 (FIG. 28) on the backside of die 520′physically attached using an electrically conductive material such as asolder preform 604. It should be noted that solder or solder preformsare described hereinbelow to electrically and physically connect metalregions together but other attachment methodologies can be used such asan electrically conductive organic adhesive, dispensed solder,conductive bumping, eutectic bonding or other known attachingmethodologies.

Turning to FIG. 36, the source lead 606 is substantially similar to theearlier embodiment and includes a pedestal 608 for receiving the frontside of die 520′. An insulating material 610 is formed on source lead606 in proximity to pedestal 608. In an embodiment of the package,insulating material 610 comprises one or more regions formed on an uppersurface of source lead 606. For example, insulating material 610comprises a ring shaped region surrounding pedestal 608 where the uppersurface of insulating material 610 is substantially planar to the uppersurface of pedestal 608. Insulating material 610 comprises electricallynon-conductive material types such as ceramics, polymers, polyimides,beryllia, aluminum nitride, glass, quartz. Insulating material 610 isattached to source lead 606 by injection molding, adhesive, or by metalconnection such as solder (to a metal layer on a bottom surface ofinsulating material 610). The inner end of gate lead 612 is electricallyconnected (e.g., by way of solder, wirebond, ribbon bond, weld, bumping,conductive adhesive, euctectic bond, etc. . . . ) to a metallizationlayer 614 on the upper surface of insulating material 610. Similarly,the inner end of drain lead 602 is mounted to a metalized region on theouter portions of insulating material 610 using an attachment method asdescribed hereinabove. The upper inner end of drain lead 602 includessolder 616. As will appear, solder 616 is used to make electricalconnection with drain stub 600. A solder preform 618 is also provided.Solder preform 618 generally corresponds with the centralizedmetallization or first electrode interconnection area 521 (FIG. 27) onthe front side of the die 520′. Solder preform 620 corresponds generallyin shape with the metallization or interconnection 522 (FIG. 27) on thefront side of the die.

An alternate version that includes more than one region of insulatingmaterial 610 is described herein to illustrate that insulating material610 is not limited to being a ring shape. A first region of insulatingmaterial 610 is formed adjacent but not surrounding pedestal 608. Theupper surface of first region of insulating material 610 issubstantially planar to the upper surface of pedestal 608. A portion ofthe die will overlie and connect to metal interconnect on the uppersurface of the first region. A second region isolating material 610comprises a ring formed on the periphery of the upper surface of sourcelead 606. Gate lead 612 and Drain lead 602 attach to the second region.A third or fourth region of isolating ring material 610 for mountingother devices can be formed on the upper surface of source lead 606 (inthe opening of the ring of the second region) for adding matchingnetworks or mounting devices that will be internal to the package. Thedevices would be interconnected to form a circuit with the die.

Turning now to FIG. 37, the subassembly of FIG. 35 is now attached tothe package base by placing the components together in the orientationshown in FIG. 37 and then heating the subassembly to melt the solder andattach the components together. In this manner, the sources of thetransistor cells of the die 520′ are coupled together in parallel by wayof source lead 606 which provides external connection to the die.Connection to the drain metallization or interconnection 501 (of thedie) is made via drain stub 600 and lead 602. Electrical connection tothe gate interconnection area 522 is provided by gate lead 612 andmetallization layer 614. Finally, a lid 622 is affixed to the upperportion of the package at the periphery of insulating material 610 asshown in FIG. 38 to provide a hermetic seal about the die 520′. Lid 622comprises a non-conductive material such as ceramic or polymer. An epoxyor adhesive is used to fasten lid 622. In an embodiment of the package,lid 622 is formed to fit around leads 602 and 612. Alternately, a gloptop or non-conductive encapsulation could also be used to seal the diefrom an external environment.

It should also be noted that, while the above examples of the packagehave been illustrated with three leads, the present inventioncontemplates more than three leads. For example, multiple gate leadscould be coupled to various points on the non-conductive member adjacentthe platform. In addition, the conductor on the non-conductive membercould connect to still other leads, or circuitry or components.

Reference to FIGS. 39 and 40 will be helpful in summarizing certainaspects of the present invention. RF power semiconductor device 900includes an array of mesh-connected transistor cells 802 a, 802 b, etc.Each cell 802 includes an annular gate region 804 which surrounds asource region 806. Control signals are applied to the gates 804 of thecells 802 by way of an electrical signal applied to gate lead 808 whichis affixed to insulating ring 910 having a conductive metallizationlayer 812 thereon. Layer 812 is connected via solder 814 to the annulargate interconnection 816 on the surface of semiconductor die 818. Thecontrol signal is fed inward from the gate interconnection 816 throughgate pathways 822 As perhaps can be seen best in FIG. 40, the gates 804of all of the transistor cells 802 are connected together in parallel.The signal flow from gate interconnection 816 is radially inwardlythrough pathways 822 which are connected to the gate regions 804 of thetransistor cells 802. The gate pathways are covered with an insulatinglayer 824 which electrically isolates the gate pathways from the sourcemetallization layer or source interconnection 826 (521 in FIG. 27).

In operation, an appropriate signal on gate lead 808 causes the channelunderneath the gate regions to become conductive. As a result, currentflows from source lead 827 (normally connected to ground) to drain lead828. In particular, the current flow is from source lead 827 throughsource interconnection 826 down through the source regions 806, thenthrough the channel region underneath the gate electrodes, then throughthe drain interconnection 819 and out through the drain lead 828.

The dielectric platform 930 and grounded shielding plate 832 are showndiagrammatically in FIG. 39. The construction and function of thedielectric platform 930 and grounded shielding plate 832 have beendescribed in detail herein.

Thermal Considerations

LDMOS, a type of prior art power transistor most prevalently used for RFamplification today, pulls heat from the bottom side of the devicethrough a heat sink, which is also an electrical source contact. Sincelarge amount of heat underneath n and p-doped regions has to betransmitted through the epitaxial and bulk silicon layers, heatdissipation is less efficient than a case in which thermal energy ispulled out from the top side of the device through a source contact, asin the preferred embodiments of this invention. In the presentinvention, due to the vertical configuration of the device, heat ismainly dissipated through ohmic contacts 711-715 on the top side of thedie as shown in FIG. 41. These ohmic contacts correspond to the metal825 (FIG. 39) extending downwardly through the vias from the larger,flat source interconnection 826 that contact the silicon of the die.

Ohmic contact 715 in the center of FIG. 41 and adjacent ohmic contacts711-714 are offset by approximately a quarter of the size of eachtransistor cell. Source region 716 and gate interconnect 717 are alsoschematically illustrated. In this instance of the present invention,each transistor cell is of equal width and height, and is somewhatsquare shaped (in the preferred embodiment the source has eight sides asdescribed hereinabove). In one embodiment, the ohmic contact of a singletransistor cell is approximately 1.8 micron by 1.8 micron square.

While the square cell configuration of FIG. 41 is acceptable for mostapplications, further improvements can be implemented if desired asshown, for example in FIG. 42. FIG. 42 is similar to FIG. 41 but thedimension of each transistor cell is rectangular, instead of square, tomaximize source ohmic contact area. In one embodiment, the dimension ofthe ohmic contact 720 of a single transistor cell is 6.0 micron by 1.8micron. Compared to a square transistor cell, a rectangular transistorcell with an ohmic contact of size 6.0 micron by 1.8 micron increasesthe source ohmic contact region by factor of 3.33. Larger source contactarea significantly improves thermal conductivity of each transistor cellby providing a wider area of thermal transfer from heated, active areasof a semiconductor die to colder metal contacts at the source.Furthermore, thermal vectors tend to crowd around the boundaries 726 ofohmic contact 720 relative to its center. Thus, heat from the center ofa source ohmic contact has a more difficult time being removed than heatgenerated near the boundary. Expanding the perimeter (larger contactarea) surrounding the ohmic contacts increases the rate at which heatcan be removed from each transistor cell through the source contactmetal. In addition, the transistor cell array has a meshed cellconfiguration with equal spacing between transistor cells, therebypreventing heat-dissipating transistor cells to create excessivehotspots caused by constructive overlap of thermal vectors from adjacentcells.

The change in the dimensions of a square ohmic contact to a rectangularohmic contact is a compromise between current density and thermalcharacteristics of the device. While some sacrifice of current densitymay occur, a surprising gain in thermal dissipation more that makes upfor the loss. For example, in one instance of the present embodiment,changing a square cell to a rectangular cell configuration resulted in a13% loss in current density yet a gain of over 40% for thermaldissipation was achieved. Higher thermal dissipation enables the presentinvention to accommodate higher power at the output, and a relativelyminor loss in current density with respect to a high gain in thermaldissipation is a good compromise.

FIG. 43 illustrates another possible improvement where the layout of theentire active area 728 of the die 730 itself has been elongated into arectangle with a large length/width ratio, preferable exceeding 10:1.The dielectric platform 733 surrounds the active area and the gateelectrode interconnection 734 is displaced and runs parallel to activearea 728. Suitable pathways (not shown) couple the gate interconnection734 with the gates in the active area 728. Connections to the drain ofthe active area can be made in any suitable manner, for example, in themanner previously discussed herein. Source metallization 732 covers theactive area and make connection to the sources of the cells in a mannerdescribed previously.

The elongated configuration of the active area 728 aids in efficientremoval of heat from the device because it provides an increasedboundary area about the periphery of the active area. In other words,heat generated in the cells in the middle of active area 728 can escapemore efficiently than, for example, when the active area approaches asquare-like configuration as show in FIG. 1. One aspect of thisembodiment is that the active area 728 has a single active area regionthat may comprise up to hundreds of thousands of transistor cells, eachof which generates a substantial amount of heat. The active area aspectratio is selected to prevent buildup of “hotspots” due to constructivethermal energy from each transistor cell thereby increasing theefficiency and reliability of the device.

Still further improvements are illustrated in FIGS. 44-46. Instead ofplacing all of the transistor cells in a single region of active area,individual separated banks 740 of active areas are connected togethersuch that the transistor cells from separated banks 740 are in parallelto perform an equivalent function of a single active area. In oneinstance of the present embodiment, 1-micron thick field oxide 741(FIGS. 45-46) separates individual active area banks 740 constructed on216 micron center to center spacings. In the present embodiment, eachbank 740 contains 8 by 21 transistor cells for a total of 168 cells perbank. The length of each bank 740 is 600 microns and the width is 160microns. Bus connections (not shown) may be provided to ensure thatbanks of active area retain identical electrical potential to each otherto prevent oscillation at the output. Gate connections 742 typicallyhave solder bumps on top and function as a single gate when connected inparallel. A metal layer 744 overlies each bank 740 and makes connectionto the sources of the transistor cells formed therein. In oneembodiment, each metal layer 744 of separated banks 740 is bumped forconnecting to a source package lead. Gate connections 742 overliedielectric platform 746 to reduce parasitic capacitance. Dielectricplatform 746 surrounds each bank of separated banks 740 to induce planarbreakdown in the transistor cells within each bank.

The thermal advantage of this embodiment—also called the “spread-cell”approach—with a group of banks spread apart by relatively largedistances (e.g., 216 microns), is significant. The source of heatresides in epitaxial layer of the die, which is well below n and p-dopedregions. Thermal energy is dissipated through source contacts, whichtypically comprise multi layers of aluminum, titanium, titanium nitride,and gold on top of banks 740. As thermal vectors rise toward the sourcecontacts, they tend to spread out, exiting the surface of the activearea at approximately 45 degree angle. The large distance of separationbetween each bank allows efficient heat dissipation without creatingexcessive hotspots due to constructive buildup of thermal energy due toclustering of transistor cells in a single region. A thermal simulationof the “spread cell” approach for a 100 watt transistor when compared anequivalent device having all the transistor cells in a single activearea region resulted in a 40% improvement in thermal efficiency.

While at least one exemplary embodiment has been presented in theforegoing detailed description, it should be appreciated that a vastnumber of variations exist. It should also be appreciated that theexemplary embodiment or exemplary embodiments are only examples, and arenot intended to limit the scope, applicability, or configuration of theinvention in any way. Rather, the foregoing detailed description willprovide those skilled in the art with a convenient road map forimplementing the exemplary embodiment or exemplary embodiments. Itshould be understood that various changes can be made in the functionand arrangement of elements without departing from the scope of theinvention as set forth in the appended claims and the legal equivalentsthereof.

What is claimed is:
 1. A method comprising: depositing a layer ofconductive material over a first surface of a semiconductor material,wherein the semiconductor material comprises a plurality of transistors,and wherein each of the plurality of transistors includes a gate, adrain region, and a source region; and coupling gates of the pluralityof transistors to each other with a mesh structure; wherein at least aportion of the mesh structure is positioned over the layer of conductivematerial, and wherein the layer of conductive material is positionedsubstantially between the mesh structure and the drain regions tothereby reduce gate-to-drain capacitance.
 2. The method of claim 1,wherein the layer of conductive material is a shield and comprisespolysilicon.
 3. The method of claim 1, further comprising coupling agate contact to the mesh structure.
 4. The method of claim 1, furthercomprising forming openings in the mesh structure, wherein the meshstructure comprises a conductive interconnect material.
 5. The method ofclaim 4, wherein the conductive interconnect material comprisespolysilicon.
 6. The method of claim 4, further comprising coupling aplurality of source interconnects to each of the source regions and tothe layer of conductive material.
 7. The method of claim 6, wherein, foreach source interconnect, at least a portion of each source interconnectis positioned in one of the openings of the mesh structure and iselectrically isolated from the mesh structure.
 8. The method of claim 1,wherein the plurality of transistors comprises vertical transistors. 9.A method comprising: forming a plurality of transistors, wherein eachtransistor of the plurality of transistors comprises a gate, a drainregion, and a source region, and wherein the source regions and at leasta portion of the drain regions are in a semiconductor material; forminga gate interconnect layer to couple the gates of the plurality oftransistors to each other; and forming a mesh-shaped layer of conductivematerial over a first surface of the semiconductor materialsubstantially between the drain region and the gate interconnect layerto thereby reduce gate-to-drain capacitance.
 10. The method of claim 9,wherein the mesh-shaped layer of conductive material is a layer ofpolysilicon, and wherein the semiconductor material comprises anepitaxial layer.
 11. The method of claim 9, further comprising formingopenings in the mesh-shaped layer of conductive material, wherein themesh-shaped layer of conductive material comprises a conductiveinterconnect material.
 12. The method of claim 9, further comprisingcoupling a metal source interconnect to at least one source region ofthe plurality of transistors, wherein the mesh-shaped layer ofconductive material is electrically coupled to the metal sourceinterconnect.
 13. The method of claim 12, further comprising forming afirst doped region of a first conductivity type extending from a firstsurface of the semiconductor material into the semiconductor material,wherein the first doped region is directly connected to the mesh-shapedlayer of conductive material at the first surface of the semiconductormaterial.
 14. The method of claim 13, wherein the first region iscontiguous around a periphery of the plurality of transistors.
 15. Amethod comprising: forming a plurality of transistors, wherein eachtransistor of the plurality of transistors comprises a gate, a drainregion, and a source region, and wherein the source regions and at leasta portion of the drain regions are formed in a semiconductor material;coupling the gates of the plurality of transistors to each other with amesh structure; forming a layer of conductive material over a firstsurface of the semiconductor material, wherein at least a portion of themesh structure is positioned over the layer of conductive material, andwherein the layer of conductive material is positioned substantiallybetween the mesh structure and the drain regions to thereby reducegate-to-drain capacitance; and coupling a gate contact to the meshstructure, wherein the gate contact comprises a gate interconnectionthat is positioned external to the mesh structure and that completelysurrounds the mesh structure, and wherein the gate contact is coupled tothe gates of the plurality of transistors of the mesh structure via oneor more gate pathways.
 16. The method of claim 15, further comprisingforming a dielectric structure extending from a first surface of thesemiconductor material into the semiconductor material, wherein the gatecontact is disposed over the dielectric structure.
 17. The method ofclaim 15, wherein the layer of conductive material is a shield andcomprises polysilicon.
 18. The method of claim 15, further comprisingforming openings in the mesh structure, wherein the mesh structurecomprises a conductive interconnect material.
 19. The method of claim18, wherein the conductive interconnect material comprises polysilicon.20. The method of claim 18, further comprising coupling a plurality ofsource interconnects to each of the source regions and to the layer ofconductive material.